Solution-processable, low-voltage, and high-performance monolayer field-effect transistors with aqueous stability and high sensitivity.

Adv Mater

Center for Nanochemistry, Beijing National Laboratory for Molecular Sciences, State Key Laboratory for Structural, Chemistry of Unstable and Stable Species, College of Chemistry and Molecular Engineering, Peking University, Beijing, 100871, PR China.

Published: March 2015

Low-voltage, low-cost, high-performance monolayer field-effect transistors are demonstrated, which comprise a densely packed, long-range ordered monolayer spin-coated from core-cladding liquid-crystalline pentathiophenes and a solution-processed high-k HfO2 -based nanoscale gate dielectric. These monolayer field-effect transistors are light-sensitive and are able to function as reporters to convert analyte binding events into electrical signals with ultrahigh sensitivity (≈10 ppb).

Download full-text PDF

Source
http://dx.doi.org/10.1002/adma.201405378DOI Listing

Publication Analysis

Top Keywords

monolayer field-effect
12
field-effect transistors
12
high-performance monolayer
8
solution-processable low-voltage
4
low-voltage high-performance
4
monolayer
4
transistors aqueous
4
aqueous stability
4
stability high
4
high sensitivity
4

Similar Publications

Post-Treatment of Monolayer MoS Field-Effect Transistors with HO Vapor: Alleviation of Remote Channel Doping.

ACS Appl Mater Interfaces

January 2025

School of Advanced Materials Science and Engineering, Sungkyunkwan University, Suwon 16419, Republic of Korea.

Atomic layer deposition (ALD) of high-k dielectric films on MoS channels can lead to inadvertent remote electron doping of channels owing to nonequilibrium ALD conditions, such as the low temperatures and short purge times required for pinhole-free coating, as well as the weak physical adsorption of ALD precursors on MoS. In this study, we propose the application of a simple and effective HO vapor post-treatment (HO PT) at 100 °C immediately after complete integration of bottom- and top-gate monolayer MoS field-effect transistors (FETs), to address the inadvertent channel doping effect. When HO PT was applied to bottom-gate monolayer MoS FETs with an ALD-AlO passivation layer, the mitigation of channel doping was confirmed through electrical and optical measurements.

View Article and Find Full Text PDF

High-performance 2D electronic devices enabled by strong and tough two-dimensional polymer with ultra-low dielectric constant.

Nat Commun

December 2024

Department of Materials Science and NanoEngineering and the Rice Advanced Materials Institute, Rice University, Houston, TX, 77005, USA.

As the feature size of microelectronic circuits is scaling down to nanometer order, the increasing interconnect crosstalk, resistance-capacitance (RC) delay and power consumption can limit the chip performance and reliability. To address these challenges, new low-k dielectric (k < 2) materials need to be developed to replace current silicon dioxide (k = 3.9) or SiCOH, etc.

View Article and Find Full Text PDF

Highly Strained Polymeric Monolayer Stacked for Wafer-Scale and Transferable Nanodielectrics.

ACS Nano

December 2024

Key Laboratory of Mesoscopic Chemistry of MOE, School of Chemistry and Chemical Engineering, Nanjing University, Nanjing, Jiangsu, 210023, China.

As the keystones of molecular electronics, high-quality nanodielectric layers are challenging to assemble due to the strictest criteria for their reliability and uniformity over a large area. Here, we report a strained poly(4-vinylphenol) monolayer, ready to be stacked to form defect-free wafer-scale nanodielectrics. The thickness of the nanodielectrics can be precisely adjusted in integral multiples of the 1.

View Article and Find Full Text PDF

Highly Oriented WS Monolayers for High-Performance Electronics.

Adv Mater

December 2024

School of Electronic Science and Engineering, College of Engineering and Applied Sciences, National Laboratory of Solid-State Microstructures, and Collaborative Innovation Center of Advanced Microstructure, Nanjing University, Nanjing, 210023, China.

2D transition-metal dichalcogenide (TMDC) semiconductors represent the most promising channel materials for post-silicon microelectronics due to their unique structure and electronic properties. However, it remains challenging to synthesize wide-bandgap TMDCs monolayers featuring large areas and high performance simultaneously. Herein, highly oriented WS monolayers are reproducibly synthesized through a templated growth strategy on vicinal C/A-plane sapphire wafers.

View Article and Find Full Text PDF

Liquid/Liquid Interfacial Assembly of Poly(methyl methacrylate)-Grafted Nanoparticles into Superlattice Monolayers and Their Application as Floating Gates for High Performance Memory.

ACS Appl Mater Interfaces

January 2025

Key Laboratory of Materials Chemistry for Energy Conversion and Storage of Ministry of Education (HUST), State Key Laboratory of Materials Processing and Die & Mold Technology, and Hubei Key Laboratory of Materials Chemistry and Service Failure, School of Chemistry and Chemical Engineering, Huazhong University of Science and Technology (HUST), Wuhan 430074, China.

Polymer/gold nanoparticle (AuNP) composites have been utilized as floating gates to enhance the performance of memory devices. However, these devices typically exhibit a low ON/OFF drain current ratio (/) and unstable charge trapping, attributed to the poorly defined arrangement of AuNPs within the composite floating gate. To address these limitations, this study employs poly(methyl methacrylate)-grafted AuNPs (Au@PMMA) as building blocks for the fabrication of monolayered superlattice films with a highly ordered structure via liquid/liquid interfacial assembly.

View Article and Find Full Text PDF

Want AI Summaries of new PubMed Abstracts delivered to your In-box?

Enter search terms and have AI summaries delivered each week - change queries or unsubscribe any time!