In this paper, we present a real-time embedded implementation of the binary masking algorithm, which has been shown to significantly improve speech-in-noise intelligibility. Our real-time implementation relies on a balance of parallel processing and hardware pipelining. We have tested and evaluated our implementation on a Spartan 3A FPGA. The measured latency was 8.5 ms . The highest measured improvement in short-time objective intelligibility was 85%.
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| http://dx.doi.org/10.1109/TBCAS.2013.2281728 | DOI Listing |
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