Thin-film transistor (TFT) is a key component of active-matrix flat-panel displays (AMFPDs). These days, the low-temperature poly silicon (LTPS) TFTs are to match with advanced AMFPDs such as the active matrix organic light-emitting diode (AMOLED) display, because of their high mobility for fast pixel switching. However, the manufacturing process of LTPS TFT is quite complicated, costly, and scale-limited. Amorphous oxide semiconductor (AOS) TFT technology is another candidate, which is as simple as that of conventioanl amorphous (a)-Si TFTs in fabrication but provides much superior device performances to those of a-Si TFTs. Hence, various AOSs have been compared with LTPS for active channel layer of the advanced TFTs, but have always been found to be relatively inferior to LTPS. In the present work, we clear the persistent inferiority, innovating the device performaces of a-IZO TFT by adopting a self-aligned coplanar top-gate structure and modifying the surface of a-IZO material. Herein, we demonstrate a high-performance simple-processed a-IZO TFT with mobility of ∼157 cm(2) V(-1) s(-1), SS of ∼190 mV dec(-1), and good bias/photostabilities, which overall surpass the performances of high-cost LTPS TFTs.
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http://dx.doi.org/10.1021/am401128p | DOI Listing |
Micromachines (Basel)
May 2022
School of Electronic and Computer Engineering, Peking University, Shenzhen 518055, China.
The low-temperature poly-Si oxide (LTPO) backplane is realized by monolithically integrating low-temperature poly-Si (LTPS) and amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) in the same display backplane. The LTPO-enabled dynamic refreshing rate can significantly reduce the display's power consumption. However, the essential hydrogenation of LTPS would seriously deteriorate AOS TFTs by increasing the population of channel defects and carriers.
View Article and Find Full Text PDFMicromachines (Basel)
December 2021
Graduate Institute of Electro-Optical Engineering, National Taiwan University of Science and Technology, No. 43, Sec. 4, Keelung Rd., Da'an Dist., Taipei City 106, Taiwan.
A new low-frame-rate active-matrix organic light-emitting diode (AMOLED) pixel circuit with low-temperature poly-Si and oxide (LTPO) thin-film transistors (TFTs) for portable displays with high pixel density is reported. The proposed pixel circuit has the excellent ability to compensate for the threshold voltage variation of the driving TFT (ΔV). By the results of simulation based on a fabricated LTPS TFT and a-IZTO TFT, we found that the error rates of the OLED current were all lower than 2.
View Article and Find Full Text PDFMicromachines (Basel)
June 2021
Department of Electrical Engineering, Pohang University of Science and Technology, Pohang 37673, Korea.
We present the fabrication and electrical characteristics of nanonet-channel (NET) low-temperature polysilicon channel (LTPS) thin-film transistors (TFTs) using a nanosphere-assisted patterning (NAP) technique. The NAP technique is introduced to form a nanonet-channel instead of the electron beam lithography (EBL) or conventional photolithography method. The size and space of the holes in the nanonet structure are well controlled by oxygen plasma treatment and a metal lift-off process.
View Article and Find Full Text PDFSci Rep
April 2021
Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon-si, 16419, Korea.
In this paper, we investigate the V shift of p-type LTPS TFTs fabricated on a polyimide (PI) and glass substrate considering charging phenomena. The V of the LTPS TFTs with a PI substrate positively shift after a bias temperature stress test. However, the V with a glass substrate rarely changed even with increasing stress.
View Article and Find Full Text PDFNanotechnology
October 2020
ICT Convergence Technology for Health & Safety and Department of Electronics and Information Engineering, Korea University, Sejong 30019, Republic of Korea.
The carrier transport of p-type low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) on flexible substrate has been intensively studied and compared to that on glass substrate in order to improve device performance. To investigate the origin of carrier transport on different substrates, temperature dependent characterizations are carried out for electrical device parameters such as threshold voltage (V ), subthreshold swing (SS), on-current (I ) and effective carrier mobility (μ ). The poly-Si grain size L and the barrier height E between grain boundaries are well known to be the main parameters to determine transport in polycrystalline silicon and can be extracted based on the polycrystalline mobility model.
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