We investigate the bias-stress effect in field-effect transistors (FETs) consisting of 1,2-ethanedithiol-treated PbS quantum dot (QD) films as charge transport layers in a top-gated configuration. The FETs exhibit ambipolar operation with typical mobilities on the order of μ(e) = 8 × 10(-3) cm(2) V(-1) s(-1) in n-channel operation and μ(h) = 1 × 10(-3) cm(2) V(-1) s(-1) in p-channel operation. When the FET is turned on in n-channel or p-channel mode, the established drain-source current rapidly decreases from its initial magnitude in a stretched exponential decay, manifesting the bias-stress effect. The choice of dielectric is found to have little effect on the characteristics of this bias-stress effect, leading us to conclude that the associated charge-trapping process originates within the QD film itself. Measurements of bias-stress-induced time-dependent decays in the drain-source current (I(DS)) are well fit to stretched exponential functions, and the time constants of these decays in n-channel and p-channel operation are found to follow thermally activated (Arrhenius) behavior. Measurements as a function of QD size reveal that the stressing process in n-channel operation is faster for QDs of a smaller diameter while stress in p-channel operation is found to be relatively invariant to QD size. Our results are consistent with a mechanism in which field-induced nanoscale morphological changes within the QD film result in screening of the applied gate field. This phenomenon is entirely recoverable, which allows us to repeatedly observe bias stress and recovery characteristics on the same device. This work elucidates aspects of charge transport in chemically treated lead chalcogenide QD films and is of relevance to ongoing investigations toward employing these films in optoelectronic devices.
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Phys Rev Lett
September 2024
MIT Lincoln Laboratory, Lexington, Massachusetts, USA.
We introduce a new output amplifier for fully depleted thick p-channel CCDs based on double-gate MOSFETs. The charge amplifier is an n-type MOSFET specifically designed and operated to couple the fully depleted CCD with high charge-transfer efficiency. The junction coupling between the CCD and MOSFET channels has enabled high sensitivity, demonstrating readout noise of 0.
View Article and Find Full Text PDFNanoscale Horiz
October 2024
Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), 77, Cheongam-ro, Nam-gu, Pohang-si, Gyeongsangbuk-do 37673, Republic of Korea.
Recently, tellurium (Te) has been proposed as a promising p-type material; however, even the state-of-the-art results couldn't overcome the critical roadblocks for its practical applications, such as large - hysteresis and high off-state leakage current. We developed a novel Te atomic layer deposition (ALD) process combined with a TeO seed layer and AlO passivation to detour the limitations of p-type Te semiconducting materials. Also, we have identified the origins of high hysteresis and off current using the 77 K operation study and passivation process optimization.
View Article and Find Full Text PDFACS Appl Mater Interfaces
August 2024
Department of Electrical and Computer Engineering, College of Design and Engineering, National University of Singapore, 4 Engineering Drive 3, Singapore 117583, Singapore.
The process development and optimization of p-type semiconductors and p-channel thin-film transistors (TFTs) are essential for the development of high-performance circuits. In this study, the Br-doped CuI (CuIBr) TFTs are proposed by the solution process to control copper vacancy generation and suppress excess holes formation in p-type CuI films and improve current modulation capabilities for CuI TFTs. The CuIBr films exhibit a uniform surface morphology and good crystalline quality.
View Article and Find Full Text PDFNanomaterials (Basel)
March 2024
Department of Electrical Engineering, Korea University, 145 Anam-ro, Seongbuk-gu, Seoul 02841, Republic of Korea.
In this study, we examine the electrical characteristics of triple-gate feedback field-effect transistors (TG FBFETs) over a temperature range of -200 °C to 280 °C. With increasing temperature from 25 °C to 280 °C, the thermally generated charge carriers increase in the channel regions such that a positive feedback loop forms rapidly. Thus, the latch-up voltage shifts from -1.
View Article and Find Full Text PDFNano Lett
January 2024
Key Laboratory for Micro/Nano Optoelectronic Devices of Ministry of Education and Hunan Provincial Key Laboratory of Low-Dimensional Structural Physics and Devices, School of Physics and Electronics, Hunan University, Changsha 410082, China.
Metal oxide semiconductor (MOS)-based complementary thin-film transistor (TFT) circuits have broad application prospects in large-scale flexible electronics. To simplify circuit design and increase integration density, basic complementary circuits require both p- and n-channel transistors based on an individual semiconductor. However, until now, no MOSs that can simultaneously show p- and n-type conduction behavior have been reported.
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