Effects of device and peripheral parameters on transconductance of silicon nanowire transistors.

This paper presents a general analysis over the transconductance function in silicon nanowire transistors (SNWTs). The transconductance function in SNWTs has been well-discussed and the relation between this function and the physical and peripheral parameters of the SNWT has been precisely investigated. The transconductance expression has been derived as a function of device parameters (e.g., oxide capacitor, electron effective-mass) and applied voltage biases, which helps to understand the essential physics of one-dimensional (1D) nanowire FETs and to interpret numerical simulation results. These simulations demonstrate the transconductance formulation as a function of environmental temperature, voltage biases and oxide layer thickness.