A compact 4 × 25 Gbps optical transceiver has been fabricated for an optical backplane system, which consists of a 4 × 25 Gbps DFB-LD array, a 4 × 25 Gbps PIN-PD array, and a CMOS transceiver chip. These are directly mounted on 9 × 14 mm(2) multi-layer ceramic package with an electromagnetic shield structure to suppress inner-channel crosstalk effectively. The transceiver includes an analog front-end as well as an electrical interface function to interface with the switch LSI or CPU. Power consumption was as low as 20 mW/Gbps, and a transmission experiment was successfully conducted at 25 Gbps.
Download full-text PDF |
Source |
|---|---|
| http://dx.doi.org/10.1364/OE.19.00B777 | DOI Listing |
Publication Analysis
Top Keywords
cmos transceiver
8
optical backplane
8
backplane system
8
100-gbps cmos
4
transceiver
4
transceiver multilane
4
multilane optical
4
system cm2
4
cm2 footprint
4
footprint compact
4
Similar Publications
Want AI Summaries of new PubMed Abstracts delivered to your In-box?
Enter search terms and have AI summaries delivered each week - change queries or unsubscribe any time!