The analysis of the P-wave on surface ECG is widely used to assess the risk of atrial arrhythmias. In order to provide reliable results, the automatic analysis of the P-wave must be precise and reliable and must take into account technical aspects, one of those being the resolution of the acquisition system. The aim of this note is to investigate the effects of the amplitude resolution of ECG acquisition systems on the P-wave analysis. Starting from ECG recorded by an acquisition system with a less significant bit (LSB) of 31 nV (24 bit on an input range of 524 mVpp), we reproduced an ECG signal as acquired by systems with lower resolution (16, 15, 14, 13 and 12 bit). We found that, when the LSB is of the order of 128 µV (12 bit), a single P-wave is not recognizable on ECG. However, when averaging is applied, a P-wave template can be extracted, apparently suitable for the P-wave analysis. Results obtained in terms of P-wave duration and morphology revealed that the analysis of ECG at lowest resolutions (from 12 to 14 bit, LSB higher than 30 µV) could lead to misleading results. However, the resolution used nowadays in modern electrocardiographs (15 and 16 bit, LSB <10 µV) is sufficient for the reliable analysis of the P-wave.

Download full-text PDF

Source
http://dx.doi.org/10.1088/0967-3334/33/2/N11DOI Listing

Publication Analysis

Top Keywords

bit lsb
16
analysis p-wave
12
p-wave analysis
12
resolution ecg
8
ecg acquisition
8
acquisition systems
8
p-wave
8
acquisition system
8
analysis
6
ecg
6

Similar Publications

Steganography is used to hide sensitive types of data including images, audio, text, and videos in an invisible way so that no one can detect it. Image-based steganography is a technique that uses images as a cover media for hiding and transmitting sensitive information over the internet. However, image-based steganography is a challenging task due to transparency, security, computational efficiency, tamper protection, payload, etc.

View Article and Find Full Text PDF

To further meet the large capacity, high spectrum efficiency (SE), reduce the signal-signal beat interference (SSBI) of the independent dual single sideband (ISB) system and the complexity of the receiver, we propose an iterative signal-signal beat interference counteraction (ISSBIC) algorithm to suppress SSBI. The 16-Gbps left sideband and the 16-Gbps right sideband signals in the ISB system are quadrature phase-shift keying (QPSK) modulated. After standard single-mode fiber (SSMF) transmission, the LSB and RSB signals are synthesized to a 16-quadrature amplitude modulation (QAM) signal after conversion through the photodetector (PD) square law.

View Article and Find Full Text PDF

In order to address the inconsistency problem caused by parasitic backend wiring among multiple ramp generators and among multiple columns in large-array CMOS image sensors (CIS), this paper proposes a high-precision compensation technology combining average voltage technology, adaptive negative feedback dynamic adjustment technology, and digital correlation double sampling technology to complete the design of an adaptive ramp signals inconsistency calibration scheme. The method proposed in this article has been successfully applied to a CIS with a pixel array of 8192(H) × 8192(V), based on the 55 nm 1P4M CMOS process, with a pixel size of 10×10μm2. The chip area is 88(H) × 89(V) mm2, and the frame rate is 10 fps.

View Article and Find Full Text PDF

Area-Efficient Mixed-Signal Time-to-Digital Converter Integration for Time-Resolved Photon Counting.

Sensors (Basel)

September 2024

Department of Electronic and Biomedical Engineering, Faculty of Physics, University of Barcelona, 08028 Barcelona, Spain.

Digital histogram generation for time-resolved measurements with single-photon avalanche diode (SPAD) sensors requires the storage of many timestamp signals. This work presents a mixed-signal time-to-digital converter (TDC) that uses analog storage to achieve an area-efficient design that can be integrated in large SPAD arrays. Fabricated using a 150 nm CMOS process, the prototype occupies an area of only 18.

View Article and Find Full Text PDF

Design of a high-precision time-to-digital converter in an Elitestek Ti60 field-programmable-gate-array.

Rev Sci Instrum

August 2024

State Key Laboratory of Particle Detection and Electronics, Department of Modern Physics, University of Science and Technology of China, Hefei 230026, China.

The time-to-digital converter (TDC) implemented in a field-programmable-gate-array has garnered widespread attention due to its flexibility and high-performance capabilities. However, issues such as non-uniformity, the bubble in the tapped delay line, and the presence of certain ultra-wide delay units can significantly compromise the precision and nonlinearity of the TDC. In this paper, we propose a high-precision TDC in an Elitestek Ti60 FPGA, effectively eliminating the adverse effects of non-uniformity, the bubble, and certain ultra-wide delay units.

View Article and Find Full Text PDF

Want AI Summaries of new PubMed Abstracts delivered to your In-box?

Enter search terms and have AI summaries delivered each week - change queries or unsubscribe any time!