An approach has been developed to produce silver nanoparticles (AgNPs) rapidly on semiconductor wafers using electrochemical deposition. The closely packed AgNPs have a density of up to 1.4 × 1011 cm-2 with good size uniformity. AgNPs retain their shape and position on the substrate when used as nanomasks for producing ultrahigh-density vertical nanowire arrays with controllable size, making it a one-step nanolithography technique. We demonstrate this method on Si/SiGe multilayer superlattices using electrochemical nanopatterning and plasma etching to obtain high-density Si/SiGe multilayer superlattice nanowires.
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http://dx.doi.org/10.1186/1556-276X-6-444 | DOI Listing |
Small
December 2024
CDL for Multi-Scale Process Modeling of Semiconductor Devices and Sensors, Institute for Microelectronics, TU Wien, Viena, 1040, Austria.
Nanotechnology
January 2023
Department of Physics, National Cheng Kung University, Tainan 70101, Taiwan.
Si/SiGe stacked multilayers are key elements in fabrication of gate-all-around (GAA) structures and improvement of electrical properties, with the evolution of the Si/SiGe interfaces playing a crucial role. In this work, a model is developed based on the simplified bond hyperpolarizability model (SBHM) to analysis the anisotropic reflective second harmonic generation (Ani-RSHG) on a three-period stacked Si/SiGemultilayer, which builds on Si(100) diamond structures. Thesymmetry of the Si(100) structure enables the second harmonic generation (SHG) contribution from the bonds to be simplified and the effective hyperpolarizabilities of the interfacial and bulk sources to be obtained.
View Article and Find Full Text PDFNanoscale Res Lett
December 2020
Key Laboratory of Microelectronic Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, 100029, People's Republic of China.
Vertical gate-all-around field-effect transistors (vGAAFETs) are considered as the potential candidates to replace FinFETs for advanced integrated circuit manufacturing technology at/beyond 3-nm technology node. A multilayer (ML) of Si/SiGe/Si is commonly grown and processed to form vertical transistors. In this work, the P-incorporation in Si/SiGe/Si and vertical etching of these MLs followed by selective etching SiGe in lateral direction to form structures for vGAAFET have been studied.
View Article and Find Full Text PDFSci Rep
November 2019
National Central University, Institute of Materials Science and Engineering, Jhongli, 32001, Taiwan, Republic of China.
Due to their inherent physical properties, thin-film Si/SiGe heterostructures have specific thermal management applications in advanced integrated circuits and this in turn is essential not only to prevent a high local temperature and overheat inside the circuit, but also generate electricity through the Seebeck effect. Here, we were able to enhance the Seebeck effect in the germanium composite quantum dots (CQDs) embedded in silicon by increasing the number of thin silicon layers inside the dot (multi-fold CQD material). The Seebeck effect in the CQD structures and multi-layer boron atomic layer-doped SiGe epitaxial films was studied experimentally at temperatures in the range from 50 to 300 K and detailed calculations for the Seebeck coefficient employing different scattering mechanisms were made.
View Article and Find Full Text PDFNano Lett
April 2017
Department of Materials Science and Engineering, University of Florida, Gainesville, Florida 32611, United States.
This Letter reports on the unusual diffusion behavior of Ge during oxidation of a multilayer Si/SiGe fin. It is observed that oxidation surprisingly results in the formation of vertically stacked Si nanowires encapsulated in defect free epitaxial strained SiGe. High angle annular dark field scanning transmission electron microscopy (HAADF-STEM) shows that extremely enhanced diffusion of Ge occurs along the vertical Si/SiO oxidizing interface and is responsible for the encapsulation process.
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