An important consideration in miniaturizing transistors is maximizing the coupling between the gate and the semiconductor channel. A nanowire with a coaxial metal gate provides optimal gate-channel coupling but has only been realized for vertically oriented nanowire transistors. We report a method for producing laterally oriented wrap-gated nanowire field-effect transistors that provides exquisite control over the gate length via a single wet etch step, eliminating the need for additional lithography beyond that required to define the source/drain contacts and gate lead. It allows the contacts and nanowire segments extending beyond the wrap-gate to be controlled independently by biasing the doped substrate, significantly improving the subthreshold electrical characteristics. Our devices provide stronger, more symmetric gating of the nanowire, operate at temperatures between 300 and 4 K, and offer new opportunities in applications ranging from studies of one-dimensional quantum transport through to chemical and biological sensing.
Download full-text PDF |
Source |
|---|---|
| http://dx.doi.org/10.1021/nl104403g | DOI Listing |
Publication Analysis
Top Keywords
Similar Publications
Achieving short high-quality gate-all-around structures for horizontal nanowire field-effect transistors.
Nanotechnology
February 2019
School of Physics, University of New South Wales, Sydney NSW 2052, Australia.
We introduce a fabrication method for gate-all-around nanowire field-effect transistors. Single nanowires were aligned perpendicular to underlying bottom gates using a resist-trench alignment technique. Top gates were then defined aligned to the bottom gates to form gate-all-around structures.
View Article and Find Full Text PDFGaN nanowire arrays with nonpolar sidewalls for vertically integrated field-effect transistors.
Nanotechnology
March 2017
Institut für Halbleitertechnik (IHT), Technische Universität Braunschweig, Hans-Sommer-Str. 66, D-38106 Braunschweig, Germany. Laboratory for Emerging Nanometrology (LENA), Technische Universität Braunschweig, Langer Kamp 6, D-38106 Braunschweig, Germany.
Vertically aligned gallium nitride (GaN) nanowire (NW) arrays have attracted a lot of attention because of their potential for novel devices in the fields of optoelectronics and nanoelectronics. In this work, GaN NW arrays have been designed and fabricated by combining suitable nanomachining processes including dry and wet etching. After inductively coupled plasma dry reactive ion etching, the GaN NWs are subsequently treated in wet chemical etching using AZ400K developer (i.
View Article and Find Full Text PDFLow Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions.
Nano Lett
April 2016
Electrical and Information Technology, ‡Solid State Physics, and §Synchrotron Radiation Research, Lund University, P.O. Box 118, SE-221 00 Lund, Sweden.
In this paper, we correlate the growth of InAs nanowires with the detailed interface trap density (Dit) profile of the vertical wrap-gated InAs/high-k nanowire semiconductor-dielectric gate stack. We also perform the first detailed characterization and optimization of the influence of the in situ doping supplied during the nanowire epitaxial growth on the sequential transistor gate stack quality. Results show that the intrinsic nanowire channels have a significant reduction in Dit as compared to planar references.
View Article and Find Full Text PDFHigh-Performance Wrap-Gated InGaAs Nanowire Field-Effect Transistors with Sputtered Dielectrics.
Sci Rep
November 2015
Department of Physics and Materials Science, City University of Hong Kong, 83 Tat Chee Avenue, Kowloon, Hong Kong.
Article Synopsis
- Wrap-gated nanowire field-effect transistors (NWFETs) show promise for low-power and high-frequency applications but face challenges due to electron scattering and complex fabrication processes.
- Researchers developed high-performance InGaAs NWFETs using conventional sputtered Al2O3 as gate dielectrics, achieving less defect trapping through prior surface chemical passivation.
- The resulting devices exhibited impressive electrical performance metrics, including a high ION/IOFF ratio and peak electron mobility, outperforming current state-of-the-art NWFETs, supporting the viability of this hybrid fabrication method for advanced electronic devices.
InAs Nanowire Transistors with Multiple, Independent Wrap-Gate Segments.
Nano Lett
May 2015
†School of Physics, University of New South Wales, Sydney, NSW 2052, Australia.
We report a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. While the step up to two independent wrap-gates requires a major change in fabrication methodology, a key advantage to this new approach, and the horizontal orientation more generally, is that achieving more than two wrap-gate segments then requires no extra fabrication steps. This is in contrast to the vertical orientation, where a significant subset of the fabrication steps needs to be repeated for each additional gate.
View Article and Find Full Text PDFWant AI Summaries of new PubMed Abstracts delivered to your In-box?
Enter search terms and have AI summaries delivered each week - change queries or unsubscribe any time!