Over the last decade, field-effect transistors (FETs) with nanoscale dimensions have emerged as possible label-free biological and chemical sensors capable of highly sensitive detection of various entities and processes. While significant progress has been made towards improving their sensitivity, much is yet to be explored in the study of various critical parameters, such as the choice of a sensing dielectric, the choice of applied front and back gate biases, the design of the device dimensions, and many others. In this work, we present a process to fabricate nanowire and nanoplate FETs with Al(2)O(3) gate dielectrics and we compare these devices with FETs with SiO(2) gate dielectrics. The use of a high-k dielectric such as Al(2)O(3) allows for the physical thickness of the gate dielectric to be thicker without losing sensitivity to charge, which then reduces leakage currents and results in devices that are highly robust in fluid. This optimized process results in devices stable for up to 8 h in fluidic environments. Using pH sensing as a benchmark, we show the importance of optimizing the device bias, particularly the back gate bias which modulates the effective channel thickness. We also demonstrate that devices with Al(2)O(3) gate dielectrics exhibit superior sensitivity to pH when compared to devices with SiO(2) gate dielectrics. Finally, we show that when the effective electrical silicon channel thickness is on the order of the Debye length, device response to pH is virtually independent of device width. These silicon FET sensors could become integral components of future silicon based Lab on Chip systems.
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http://dx.doi.org/10.1007/s10544-010-9497-z | DOI Listing |
Micromachines (Basel)
January 2025
College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China.
The short-circuit (SC) robustness of SiC MOSFETs is critical for high-power applications, yet 1.2 kV devices often struggle to meet the industry-standard SC withstand time (SCWT) under practical operating conditions. Despite growing interest in higher voltage classes, no prior study has systematically evaluated the SC performance of 1.
View Article and Find Full Text PDFMicromachines (Basel)
December 2024
High-Power Converter Systems (HLU), Technical University of Munich (TUM), 80333 Munich, Germany.
Gate dielectrics are essential components in nanoscale field-effect transistors (FETs), but they often face significant instabilities when exposed to harsh environments, such as radioactive conditions, leading to unreliable device performance. In this paper, we evaluate the performance of ultrascaled transition metal dichalcogenide (TMD) FETs equipped with vacuum gate dielectric (VGD) as a means to circumvent oxide-related instabilities. The nanodevice is computationally assessed using a quantum simulation approach based on the self-consistent solutions of the Poisson equation and the quantum transport equation under the ballistic transport regime.
View Article and Find Full Text PDFJ Am Chem Soc
January 2025
State Key Laboratory of Precision and Intelligent Chemistry, CAS Key Laboratory of Mechanical Behavior and Design of Materials, University of Science and Technology of China, Hefei, Anhui 230026, P. R. China.
Recent progress in superconductor-insulator transition has shed light on the intermediate metallic state with unique electronic inhomogeneity. The microscopic model, suggesting that carrier spatial distribution plays a decisive role in the intermediate state, has been instrumental in understanding the quantum transition. However, the narrow carrier density window in which the intermediate state exists necessitates precise control of the gate dielectric layer, presenting a challenge to in situ map the carrier spatial distribution.
View Article and Find Full Text PDFNano Lett
January 2025
Key Lab for the Physics and Chemistry of Nanodevices and Center for Carbon-based Electronics, School of Electronics, Peking University, Beijing 100871, China.
One-time programmable (OTP) memory is an essential component in chips, which has extremely high security to protect the stored critical information from being altered. However, traditional OTP memory based on the thermal breakdown of the dielectric has a large programming current, which leads to high power consumption. Here, we report a gate tunneling-induced "cold" breakdown phenomenon in carbon nanotube (CNT) field-effect transistors, and based on this we construct a "cold" fuse (C-fuse) memory where applying a mild gate voltage can break down the CNT channel without damaging the gate dielectric.
View Article and Find Full Text PDFRSC Adv
January 2025
Department of Solid State Physics and Nonlinear Physics, Faculty of Physics and Technology, AL-Farabi Kazakh National University Almaty 050040 Kazakhstan.
In this paper, Gd-doped ZrO gate dielectric films and metal-oxide-semiconductor (MOS) capacitors structured as Al/ZrGdO /Si were prepared using an ultraviolet ozone (UVO)-assisted sol-gel method. The effects of heat treatment temperature on the microstructure, chemical bonding state, optical properties, surface morphology and electrical characteristics of the ZrGdO composite films and MOS capacitors were systematically investigated. The crystalline phase of the ZrGdO films appeared only at 600 °C, indicating that Gd doping effectively inhibits the crystallization of ZrO films.
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