A fast, power-efficient electro-optical vector-by-matrix multiplier (VMM) architecture is presented. Careful design of an electrical unit supporting high-speed data transfer enables this architecture to overcome bottlenecks encountered by previous VMM architectures. Based on the proposed architecture, we present an electro-optical digital signal processing (DSP) coprocessor that can achieve a significant speedup of 2-3 orders of magnitude over existing DSP technologies and execute more than 16 teraflops. We show that it is feasible to implement the system using off-the-shelf components, analyze the performance of the architecture with respect to primitive DSP operations, and detail the use of the new architecture for several DSP applications.
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http://dx.doi.org/10.1364/josaa.26.000a11 | DOI Listing |
BMC Bioinformatics
April 2010
Department of Computer Science and Engineering, University of South Carolina, Columbia, SC, USA.
Background: Likelihood (ML)-based phylogenetic inference has become a popular method for estimating the evolutionary relationships among species based on genomic sequence data. This method is used in applications such as RAxML, GARLI, MrBayes, PAML, and PAUP. The Phylogenetic Likelihood Function (PLF) is an important kernel computation for this method.
View Article and Find Full Text PDFJ Opt Soc Am A Opt Image Sci Vis
August 2009
Department of Computer Science, Texas State University, San Marcos, TX 78666, USA.
A fast, power-efficient electro-optical vector-by-matrix multiplier (VMM) architecture is presented. Careful design of an electrical unit supporting high-speed data transfer enables this architecture to overcome bottlenecks encountered by previous VMM architectures. Based on the proposed architecture, we present an electro-optical digital signal processing (DSP) coprocessor that can achieve a significant speedup of 2-3 orders of magnitude over existing DSP technologies and execute more than 16 teraflops.
View Article and Find Full Text PDFComput Biol Med
November 1994
Biomedical Engineering Department, Faculty of Engineering, Tel Aviv University, Israel.
A real-time multichannel fetal ECG monitor based on a personal computer (PC) and a MOTOROLA DSP56001 Digital Signal CoProcessor (DSP) is introduced. The DSP board is plugged into the PC, which functions as a HOST computer. An analog 8 Leads Interface and Analog to Digital circuits module is connected to the DSP through a synchronous, optical-isolated communication channel.
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