Antireflective nanosponges are fabricated on polycrystalline silicon (poly-Si) thin films using Ag-nanoparticles (NPs) assisted etching. Crystal orientations and grain sizes of the poly-Si thin films are investigated for the poly-Si nanosponge formation and the resultant optical properties. The Ag-NPs assisted etching preferentially etches the poly-Si thin films along crystal orientation of [110]. A 400 nm thick poly-Si nanosponge reduces effective optical reflection of the poly-Si thin film with substrate crystal orientation of (110) and averaged grain size of 250 nm from 26 % to 3 % at the wavelengths ranging from 400 nm to 1000 nm. Carrier lifetimes were found to be 41 and 36 mus for poly-Si thin film and RTO-passivated nanosponges, respectively.
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http://dx.doi.org/10.1364/oe.17.004646 | DOI Listing |
Micromachines (Basel)
December 2024
International Iberian Nanotechnology Laboratory, 4715-330 Braga, Portugal.
The development of low-temperature piezoresistive materials provides compatibility with standard silicon-based MEMS fabrication processes. Additionally, it enables the use of such material in flexible substrates, thereby expanding the potential for various device applications. This work demonstrates, for the first time, the fabrication of a 200 nm polycrystalline silicon thin film through a metal-induced crystallization process mediated by an AlSiCu alloy at temperatures as low as 450 °C on top of silicon and polyimide (PI) substrates.
View Article and Find Full Text PDFMaterials (Basel)
November 2024
University of the Ryukyus, Nishihara 903-0213, Okinawa, Japan.
Sci Rep
November 2024
Electronics Engineering Institute, National Yang Ming Chiao Tung University, Hsinchu, 300, Taiwan.
Using ultraviolet (UV) annealing through wide energy bandgap HfO/SiO gate dielectric, nanosheet SnO pFET achieved hole effective mobility (µ) from 55 cm/V-s at low hole density (Q) to 13.38 cm/V-s at 5 × 10 cm Q, compared to that of 9.03 cm/V-s at 5 × 10 cm Q for SnO device without UV annealing.
View Article and Find Full Text PDFACS Appl Mater Interfaces
September 2024
Ecole Polytechnique Fédérale de Lausanne (EPFL), Institute of Electrical and Microengineering (IEM), Photovoltaics and Thin-Film Electronics Laboratory (PV-Lab), Maladière 71b, 2000 Neuchâtel, Switzerland.
Full-area passivating contacts based on SiO/poly-Si stacks are key for the new generation of industrial silicon solar cells substituting the passivated emitter and rear cell (PERC) technology. Demonstrating a potential efficiency increase of 1 to 2% compared to PERC, the utilization of n-type wafers with an n-type contact at the back and a p-type diffused boron emitter has become the industry standard in 2024. In this work, variations of this technology are explored, considering p-type passivating contacts on p-type Si wafers formed via a rapid thermal processing (RTP) step.
View Article and Find Full Text PDFMaterials (Basel)
June 2024
Institute of Technology for Carbon Neutralization, Yangzhou University, Yangzhou 225009, China.
Thin polysilicon (poly-Si)-based passivating contacts can reduce parasitic absorption and the cost of n-TOPCon solar cells. Herein, n-poly-Si layers with thicknesses of 30~100 nm were fabricated by low-pressure chemical vapor deposition (LPCVD) to create passivating contacts. We investigated the effect of n-poly-Si layer thickness on the microstructure of the metallization contact formation, passivation, and electronic performance of n-TOPCon solar cells.
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