PLL jitter reduction by utilizing a ferroelectric capacitor as a VCO timing element.

IEEE Trans Ultrason Ferroelectr Freq Control

Microelectronics Research Laboratories, Department of Electrical and Computer Engineering, University of Colorado, Colorado Springs, CO 80933-7150, USA.

Published: June 2007

Ferroelectric capacitors have steadily been integrated into semiconductor processes due to their potential as storage elements within memory devices. Polarization reversal within ferroelectric capacitors creates a high nonlinear dielectric constant along with a hysteresis profile. Due to these attributes, a phase-locked loop (PLL), when based on a ferroelectric capacitor, has the advantage of reduced cycle-to-cycle jitter. PLLs based on ferroelectric capacitors represent a new research area for reduction of oscillator jitter.

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Source
http://dx.doi.org/10.1109/tuffc.2007.363DOI Listing

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