An algorithm for implementing visual stimulators on generic computers has been developed for Brain Computer Interfaces (BCIs). It uses the hardware counter present in these systems to derive accurate timing. Simultaneous display of 20 patterns (e.g. 3×3 checkerboards) modulated at different frequencies is possible. The pattern used for stimulating the Steady State Visual Evoked Potential (SSVEP) can be changed with ease. The stimulators are evaluated using software counters. High accuracy (less than 0.73% error) and precision (0.1% coefficient of variation) is recorded for 20 patterns set with frequencies between 6 Hz and 15 Hz.
Download full-text PDF |
Source |
|---|---|
| http://dx.doi.org/10.1109/IEMBS.2005.1615698 | DOI Listing |
Publication Analysis
Top Keywords
brain computer
8
computer interfaces
8
design implementation
4
implementation high
4
high performance
4
performance visual
4
visual stimulator
4
stimulator brain
4
interfaces algorithm
4
algorithm implementing
4
Similar Publications
Want AI Summaries of new PubMed Abstracts delivered to your In-box?
Enter search terms and have AI summaries delivered each week - change queries or unsubscribe any time!