The State Transition Equation (STE) based method to automatically generate the parallel CRC circuits for any generator polynomial or required amount of parallelism is presented. The parallel CRC circuit so generated is partially optimized before being fed to synthesis tools and works properly in our LAN transceiver. Compared with the cascading method, the proposed method gives better timing results and significantly reduces the synthesis time, in particular.
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| http://dx.doi.org/10.1631/jzus.2003.0433 | DOI Listing |
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