A Novel Channel Preparation Scheme to Optimize Program Disturbance in Three-Dimensional NAND Flash Memory.

The program disturbance characteristics of three-dimensional (3D) vertical NAND flash cell array architecture pose a critical reliability challenge due to the lower unselected word line (WL) pass bias (Vpass) window. In other words, the key contradiction of program disturbance is that the operational Vpass during the program's performance cannot be too high or too low. For instance, the 3D NAND program's operation string needs a lower Vpass bias to suppress unselected WL Vpass bias-induced Fowler-Nordheim tunneling (FN tunneling), but for the inhibited string, the unselected WL needs a higher Vpass bias to suppress selected WL program bias (Vpgm)-induced FN tunneling.

Investigation of Erase Cycling Induced Joint Dummy Cell Disturbance in Dual-Deck 3D NAND Flash Memory.

To satisfy the increasing demands for more word-line (WL) layers, the dual-deck even triple-deck architecture has emerged in 3D NAND Flash. However, the new reliability issues that occurred at the joint region of two decks became a severe challenge for developing multiple-deck technology. This work reported an abnormal reliability issue introduced by erasing disturbance of the dummy WLs at the joint region (Joint-DMYs) under multiple cycling.

Activation Enhancement and Grain Size Improvement for Poly-Si Channel Vertical Transistor by Laser Thermal Annealing in 3D NAND Flash.

The bit density is generally increased by stacking more layers in 3D NAND Flash. Lowering dopant activation of select transistors results from complex integrated processes. To improve channel dopant activation, the test structure of vertical channel transistors was used to investigate the influence of laser thermal annealing on dopant activation.

A Novel Capacitorless 1T DRAM with Embedded Oxide Layer.

A novel vertical dual surrounding gate transistor with embedded oxide layer is proposed for capacitorless single transistor DRAM (1T DRAM). The embedded oxide layer is innovatively used to improve the retention time by reducing the recombination rate of stored holes and sensing electrons. Based on TCAD simulations, the new structure is predicted to not only have the characteristics of fast access, random read and integration of 4F cell, but also to realize good retention and deep scaling.

Dual-axis control of magnetic anisotropy in a single crystal CoMnSi thin film through piezo-voltage-induced strain.

Voltage controlled magnetic anisotropy (VCMA) has been considered as an effective method in traditional magnetic devices with lower power consumption. In this article, we have investigated the dual-axis control of magnetic anisotropy in CoMnSi/GaAs/PZT hybrid heterostructures through piezo-voltage-induced strain using longitudinal magneto-optical Kerr effect (LMOKE) microscopy. The major modification of in-plane magnetic anisotropy of the CoMnSi thin film is controlled obviously by the piezo-voltages of the lead zirconate titanate (PZT) piezotransducer, accompanied by the coercivity field and magnetocrystalline anisotropy significantly manipulated.

The Optimization of Gate All Around-L-Shaped Bottom Select Transistor in 3D NAND Flash Memory.

In this work, the GAA (Gate All Around) L-Shaped bottom select transistor (BSG) in 3D NAND Flash Memory has been investigated. Different methods are proposed to optimize its performance from viewpoints of process and structure. BSG in 3D NAND is a novel device structure with two connected transistors: one is horizontal MOSFET (regarded as convention MOSFET) and one is vertical MOSFET (regarded as GAA transistor).

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density.

Isolated nanographene crystals for nano-floating gate in charge trapping memory.

Graphene exhibits unique electronic properties, and its low dimensionality, structural robustness, and high work-function make it very promising as the charge storage media for memory applications. Along with the development of miniaturized and scaled up devices, nanostructured graphene emerges as an ideal material candidate. Here we proposed a novel non-volatile charge trapping memory utilizing isolate and uniformly distributed nanographene crystals as nano-floating gate with controllable capacity and excellent uniformity.

Bipolar one diode-one resistor integration for high-density resistive memory applications.

Different from conventional unipolar-type 1D-1R RRAM devices, a bipolar-type 1D-1R memory device concept is proposed and successfully demonstrated by the integration of Ni/TiOx/Ti diode and Pt/HfO2/Cu bipolar RRAM cell to suppress the undesired sneak current in a cross-point array. The bipolar 1D-1R memory device not only achieves self-compliance resistive switching characteristics by the reverse bias current of the Ni/TiOx/Ti diode, but also exhibits excellent bipolar resistive switching characteristics such as uniform switching, satisfactory data retention, and excellent scalability, which give it high potentiality for high-density integrated nonvolatile memory applications.

A study of cycling induced degradation mechanisms in Si nanocrystal memory devices.

The endurance of Si nanocrystal memory devices under Fowler-Nordheim program and erase (P/E) cycling is investigated. Both threshold voltage (V(th)) and subthreshold swing (SS) degradation are observed when using a high program or erase voltage. The change of SS is found to be proportional to the shift of V(th), indicating that the generation of interface traps plays a dominant role.

Controllable growth of nanoscale conductive filaments in solid-electrolyte-based ReRAM by using a metal nanocrystal covered bottom electrode.

Resistive memory (ReRAM) based on a solid-electrolyte insulator is a promising nanoscale device and has great potentials in nonvolatile memory, analog circuits, and neuromorphic applications. The underlying resistive switching (RS) mechanism of ReRAM is suggested to be the formation and rupture of nanoscale conductive filament (CF) inside the solid-electrolyte layer. However, the random nature of the nucleation and growth of the CF makes their formation difficult to control, which is a major obstacle for ReRAM performance improvement.