Publications by authors named "Zhongrui Xiao"

At sub-3 nm nodes, the scaling of lateral devices represented by a fin field-effect transistor (FinFET) and gate-all-around field effect transistors (GAAFET) faces increasing technical challenges. At the same time, the development of vertical devices in the three-dimensional direction has excellent potential for scaling. However, existing vertical devices face two technical challenges: "self-alignment of gate and channel" and "precise gate length control".

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Article Synopsis
  • Transistor scaling in dynamic random access memory (DRAM) is becoming challenging, pushing researchers to explore vertical devices for improved performance.
  • Many vertical devices struggle with technical issues like controlling gate length and achieving proper alignment between gate and source/drain.
  • The newly developed recrystallization-based vertical C-shaped-channel nanosheet field-effect transistors (RC-VCNFETs) exhibit strong performance, showcasing a subthreshold swing of 62.91 mV/dec and low drain-induced barrier lowering of 6.16 mV/V.
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A novel n-type nanowire/nanosheet (NW/NS) vertical sandwich gate-all-around field-effect-transistor (nVSAFET) with self-aligned and replaced high-κ metal gates (HKMGs) is presented for the first time, aiming at a 3 nm technology node and beyond. The nVSAFETs were fabricated by an integration flow of Si/SiGe epitaxy, quasi-atomic layer etching (qALE) of SiGe selective to Si, formation of SiGe/Si core/shell NS/NW structure, building of nitride dummy gate, and replacement of the dummy gate. This fabrication method is complementary metal oxide semiconductor (CMOS)-compatible, simple, and reproducible, and NWs with a diameter of 17 nm and NSs with a thickness of 20 nm were obtained.

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