Large-scale sub-5-nm vertical transistors by van der Waals integration.

Vertical field effect transistor (VFET), in which the semiconductor is sandwiched between source/drain electrodes and the channel length is simply determined by the semiconductor thickness, has demonstrated promising potential for short channel devices. However, despite extensive efforts over the past decade, scalable methods to fabricate ultra-short channel VFETs remain challenging. Here, we demonstrate a layer-by-layer transfer process of large-scale indium gallium zinc oxide (IGZO) semiconductor arrays and metal electrodes, and realize large-scale VFETs with ultra-short channel length and high device performance.

High-density vertical sidewall MoS transistors through T-shape vertical lamination.

Vertical transistors, in which the source and drain are aligned vertically and the current flow is normal to the wafer surface, have attracted considerable attention recently. However, the realization of high-density vertical transistors is challenging, and could be largely attributed to the incompatibility between vertical structures and conventional lateral fabrication processes. Here we report a T-shape lamination approach for realizing high-density vertical sidewall transistors, where lateral transistors could be pre-fabricated on planar substrates first and then laminated onto vertical substrates using T-shape stamps, hence overcoming the incompatibility between planar processes and vertical structures.

Solid-State Anion Exchange Enabled by Pluggable vdW Assembly for In Situ Halide Manipulation in Perovskite Monocrystalline Film.

The fabrication of perovskite single crystal-based optoelectronics with improved performance is largely hindered by limited processing techniques. Particularly, the local halide composition manipulation, which dominates the bandgap and thus the formation of heterostructures and emission of multiple-wavelength light, is realized via prevalent liquid- or gas-phase anion exchange with the utilization of lithography, while the monocrystalline nature is sacrificed due to polycrystalline transition in exchange with massive defects emerging, impeding carrier separation and transportation. Thus, a damage-free and lithography-free solid-state anion exchange strategy, aiming at in situ halide manipulation in perovskite monocrystalline film, is developed.

Edge-by-Edge Lateral Heterostructure through Interfacial Sliding.

van der Waals heterostructures (vdWHs) based on two-dimensional (2D) semiconductors have attracted considerable attention. However, the reported vdWHs are largely based on vertical device structure with large overlapping area, while the realization of lateral heterostructures contacted through 2D edges remains challenging and is majorly limited by the difficulties of manipulating the lateral distance of 2D materials at nanometer scale (during transfer process). Here, we demonstrate a simple interfacial sliding approach for realizing an edge-by-edge lateral contact.

Ultrashort vertical-channel MoS transistor using a self-aligned contact.

Two-dimensional (2D) semiconductors hold great promises for ultra-scaled transistors. In particular, the gate length of MoS transistor has been scaled to 1 nm and 0.3 nm using single wall carbon nanotube and graphene, respectively.

Ag-Assisted Dry Exfoliation of Large-Scale and Continuous 2D Monolayers.

Two-dimensional (2D) semiconductors have generated considerable attention for high-performance electronics and optoelectronics. However, to date, it is still challenging to mechanically exfoliate large-area and continuous monolayers while retaining their intrinsic properties. Here, we report a simple dry exfoliation approach to produce large-scale and continuous 2D monolayers by using a Ag film as the peeling tape.

Defect Engineering of Controllable Carrier Types in WSe for Homomaterial Inverters and Self-Powered Photodetectors.

WSe has a high mobility of electrons and holes, which is an ideal choice as active channels of electronics in extensive fields. However, carrier-type tunability of WSe still has enormous challenges, which are essential to overcome for practical applications. In this work, the direct growth of n-doped few-layer WSe is realized via defect engineering.

Realizing On/Off Ratios over 10 for Sub-2 nm Vertical Transistors.

Vertical transistors hold promise for the development of ultrascaled transistors. However, their on/off ratios are limited by a strong source-drain tunneling current in the off state, particularly for vertical devices with a sub-5 nm channel length. Here, we report an approach for suppressing the off-state tunneling current by designing the barrier height via a van der Waals metal contact.

High-Density Vertical Transistors with Pitch Size Down to 20 nm.

Vertical field effect transistors (VFETs) have attracted considerable interest for developing ultra-scaled devices. In particular, individual VFET can be stacked on top of another and does not consume additional chip footprint beyond what is needed for a single device at the bottom, representing another dimension for high-density transistors. However, high-density VFETs with small pitch size are difficult to fabricate and is largely limited by the trade-offs between drain thickness and its conductivity.

Mobility Enhancement of Strained MoS Transistor on Flat Substrate.

Strain engineering has been proposed as a promising method to boost the carrier mobility of two-dimensional (2D) semiconductors. However, state-of-the-art straining approaches are largely based on putting 2D semiconductors on flexible substrates or rough substrate with nanostructures (., nanoparticles, nanorods, ripples), where the observed mobility change is not only dependent on channel strain but could be impacted by the change of dielectric environment as well as rough interface scattering.

Wafer-scale high-κ dielectrics for two-dimensional circuits via van der Waals integration.

The practical application of two-dimensional (2D) semiconductors for high-performance electronics requires the integration with large-scale and high-quality dielectrics-which however have been challenging to deposit to date, owing to their dangling-bonds-free surface. Here, we report a dry dielectric integration strategy that enables the transfer of wafer-scale and high-κ dielectrics on top of 2D semiconductors. By utilizing an ultra-thin buffer layer, sub-3 nm thin AlO or HfO dielectrics could be pre-deposited and then mechanically dry-transferred on top of MoS monolayers.

Wafer-scale and universal van der Waals metal semiconductor contact.

Van der Waals (vdW) metallic contacts have been demonstrated as a promising approach to reduce the contact resistance and minimize the Fermi level pinning at the interface of two-dimensional (2D) semiconductors. However, only a limited number of metals can be mechanically peeled and laminated to fabricate vdW contacts, and the required manual transfer process is not scalable. Here, we report a wafer-scale and universal vdW metal integration strategy readily applicable to a wide range of metals and semiconductors.

Ultimate low leakage and EOT of high-dielectric using transferred metal electrode.

The increase of gate leakage current when the gate dielectric layer is thinned is a key issue for device scalability. For scaling down the integrated circuits, a thin gate dielectric layer with a low leakage current is essential. Currently, changing the dielectric layer material or enhancing the surface contact between the gate dielectric and the channel material is the most common way to reduce gate leakage current in devices.

Nonlinear co-generation of graphene plasmons for optoelectronic logic operations.

Surface plasmons in graphene provide a compelling strategy for advanced photonic technologies thanks to their tight confinement, fast response and tunability. Recent advances in the field of all-optical generation of graphene's plasmons in planar waveguides offer a promising method for high-speed signal processing in nanoscale integrated optoelectronic devices. Here, we use two counter propagating frequency combs with temporally synchronized pulses to demonstrate deterministic all-optical generation and electrical control of multiple plasmon polaritons, excited via difference frequency generation (DFG).

Realization of Ultra-Scaled MoS Vertical Diodes via Double-Side Electrodes Lamination.

Schottky diode is the fundamental building blocks for modern electronics and optoelectronics. Reducing the semiconductor layer thickness could shrink the vertical size of a Schottky diode, improving its speed and integration density. Here, we demonstrate a new approach to fabricate a Schottky diode with ultrashort physical length approaching atomic limit.

Strain-Plasmonic Coupled Broadband Photodetector Based on Monolayer MoS.

2D Semiconductors are promising in the development of next-generation photodetectors. However, the performances of 2D photodetectors are largely limited by their poor light absorption (due to ultrathin thickness) and small detection range (due to large bandgap). To overcome the limitations, a strain-plasmonic coupled 2D photodetector is designed by mechanically integrating monolayer MoS on top of prefabricated Au nanoparticle arrays.

Dry Exfoliation of Large-Area 2D Monolayer and Heterostructure Arrays.

Two-dimensional (2D) semiconductors have attracted considerable attention in recent years. However, to date, there is still no effective approach to produce large-scale monolayers while retaining their intrinsic properties. Here, we report a simple mechanical exfoliation method to produce large-scale and high-quality 2D semiconductors, by designing an atomically flat Au-mesh film as the peeling tape.

Reconfigurable electronics by disassembling and reassembling van der Waals heterostructures.

Van der Waals heterostructures (vdWHs) have attracted tremendous interest owing to the ability to assemble diverse building blocks without the constraints of lattice matching and processing compatibility. However, once assembled, the fabricated vdWHs can hardly be separated into individual building blocks for further manipulation, mainly due to technical difficulties in the disassembling process. Here, we show a method to disassemble the as-fabricated vdWHs into individual building blocks, which can be further reassembled into new vdWHs with different device functionalities.

The late parietal event-related potential component is hierarchically sensitive to chunk tightness during chunk decomposition.

The current study analyzed event-related potentials (ERPs) associated with visuo-spatial transformation in order to examine how "chunk tightness" affects the difficulty of chunk decomposition problems. Participants completed a Chinese character decomposition task in three conditions according to the tightness of the to-be-decomposed chunk (tight vs. medium vs.

The Effect of Working Memory Updating Ability on Spatial Insight Problem Solving: Evidence From Behavior and Eye Movement Studies.

It still remains uncertain whether working memory updating ability influences spatial insight problem solving and whether working memory updating ability plays a role in the representation restructuring phase. The current study explored the correlation of working memory updating ability and spatial insight problem solving by behavior and eye movement experiments, and the results showed that high working memory updating ability individuals spend significant shorter time to solve spatial insight problem than low working memory updating ability individuals. For participants with high or low working memory updating ability, the underlying mechanism of spatial insight problem solving is sudden rather than incremental, which demonstrated that the working memory updating ability did not influence the representation restructuring phase.

The Effect of the Embodied Guidance in the Insight Problem Solving: An Eye Movement Study.

Insight is an important cognitive process in creative thinking. The present research applied embodied cognitive perspective to explore the effect of embodied guidance on insight problem solving and its underlying mechanisms by two experiments. Experiment 1 used the matchstick arithmetic problem to explore the role of embodied gestures guidance in problem solving.