Investigation of the Electrical Coupling Effect for Monolithic 3-Dimensional Nonvolatile Memory Consisting of a Feedback Field-Effect Transistor Using TCAD.

In this study, the electrical characteristics and electrical coupling effect for monolithic 3-dimensional nonvolatile memory consisting of a feedback field-effect transistor (M3D-NVM-FBFET) were investigated using technology computer-aided design. The M3D-NVM-FBFET consists of an N-type FBFET with an oxide-nitride-oxide layer and a metal-oxide-semiconductor FET (MOSFET) in the top and bottom tiers, respectively. For the memory simulation, the programming and erasing voltages were applied at 18 and -18 V for 1 μs, respectively.

Effects of Thermal Treatment on DC Voltage-Driven Color Conversion in Organic Light-Emitting Diode.

A DC voltage-dependent color-tunable organic light-emitting diode (CTOLED) was proposed for lighting applications. The CTOLED consists of six consecutive organic layers: the hole injection layer, the hole transport layer (HTL), two emission layers (EMLs), a hole blocking layer (HBL), and an electron transport layer (ETL). Only one metal-free phthalocyanine (HPc) layer with a thickness of 5 nm was employed as the EML in the CTOLED on a green organic light-emitting diode (OLED) structure using tris (8-hydroxyquinoline) aluminum (III) (Alq).

A Monolithic 3-Dimensional Static Random Access Memory Containing a Feedback Field Effect Transistor.

A monolithic three-dimensional integrated static random access memory containing a feedback field effect transistor (M3D-FBFET-SRAM) was proposed. The M3D-FBFET-SRAM cell consists of one metal oxide semiconductor field effect transistor (MOSFET) and one FBFET, and each transistor is located on the top tier and one on the bottom tier in a monolithic 3D integration, respectively. The electrical characteristics and operation of the NFBFET in the M3D-FBFET-SRAM cell were investigated using a TCAD simulator.

An Investigation of the Effect of the Work-Function Variation of a Monolithic 3D Inverter Stacked with MOSFETs.

The effect of the work-function variation (WFV) of metal-oxide-semiconductor field-effect transistor (MOSFET) gates on a monolithic 3D inverter (M3DINV) structure is investigated in the current paper. The M3DINV has a structure in which MOSFETs are sequentially stacked. The WFV effect of the top- and bottom-tier gates on the M3DINV is investigated using technology computer-aided design (TCAD) and a Monte-Carlo sampling simulation of TCAD.

Investigation of Tunneling Effect for a N-Type Feedback Field-Effect Transistor.

In this paper, the tunneling effect for a N-type feedback field-effect transistor (NFBFET) was investigated. The NFBFET has highly doped N-P junction in the channel region. When drain-source voltage is applied at the NFBFET, the aligning between conduction band of N-region and valence band of P-region occur, and band-to-band tunneling (BTBT) current can be formed on surface region of N-P junction in the channel of the NFBFET.

Macro-Modeling for N-Type Feedback Field-Effect Transistor for Circuit Simulation.

In this study, we propose an improved macro-model of an N-type feedback field-effect transistor (NFBFET) and compare it with a previous macro-model for circuit simulation. The macro-model of the NFBFET is configured into two parts. One is a charge integrator circuit and the other is a current generator circuit.

Electrical Coupling for Monolithic 3-D Integrated Circuit Consisting of Feedback Field-Effect Transistors.

In this study, for two cases of monolithic 3-dimensional integrated circuit (M3DIC) consisting of vertically stacked feedback field-effect transistors (FBFETs), the variation of electrical characteristics of the FBFET was presented in terms of electrical coupling by using technology computer aided design (TCAD) simulation. In the Case 1, the M3DIC was composed with an -type FBFET in an upper tier (tier2) and a -type FBFET in a lower tier (tier1), and in the Case 2, it was composed with the FBFETs of opposite type of the Case 1 on each tier. To utilize the FBFET as a logic device, the study on optimal structure of FBFET was first performed in terms of reducing a memory window.

Interface Trap Charge Effects of Monolithic 3D Junctionless Field-Effect Transistors (JLFET) Inverter.

We investigated the effect of the interface trap charge in a monolithic three-dimensional inverter structure composing of JLFETs (M3DINV-JLFET), using the interface trap charge distribution extracted in the previous study. The effect of interface trap charge was compared with a conventional M3DINV composing of MOSFETs (M3DINV-MOSFETs) by technology computer-aided design simulation. When the interface trap charges in both M3DINV-JLFET and M3DINV-MOSFET are added, the threshold voltages, on-current levels, and subthreshold swings of both JLFETs and MOSFETs increase, decrease, and increase, respectively, and switching voltages and propagation delays of M3DINV are shifted and increased, respectively.

Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs.

The junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed of JLFETs (M3DIC-JLFET). We validated the model by extracting the model parameters and comparing the simulation results of the technology computer-aided design and the Synopsys HSPICE circuit simulator.

Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation.

The optimal structure and process for the feedback field-effect transistor (FBFET) to operate as a logic device are investigated by using a technology computer-aided design mixed-mode simulator. To minimize the memory window of the FBFET, the channel length (), thickness of silicon body (), and doping concentration () of the channel region below the gate are adjusted. As a result, the memory window increases as and increase, and the memory window is minimum when is approximately 9 × 10 cm.

Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory.

In order to simulate a circuit by applying various logic circuits and full chip using the HSPICE model, which can consider electrical coupling proposed in the previous research, it is investigated whether additional electrical coupling other than electrical coupling by top and bottom layer exists. Additional electrical coupling were verified through device simulation and confirmed to be blocked by heavily doped source/drain. Comparing the HSPICE circuit simulation results using the newly proposed monolithic 3D NAND (M3DNAND) structure in the technology computer-aided design (TCAD) mixed-mode and monolithic 3D inverter (M3DINV) unit cell model was once more verified.

Si/Ge Hetero Tunnel Field-Effect Transistor with Junctionless Channel Based on Nanowire.

A Si/Ge hetero tunnel field-effect transistor (TFET) with junctionless channel based on nanowire (JLNW-TFET) is proposed, and its electrical performance and dependency of natural parameters are investigated. The JLNW-TFET is operated by compensating each demerit of the following two mechanisms: thermionic generation of junctionless field-effect transistor (JLFET) and band to band tunneling (BTBT) generation of tunnel field-effect transistor (TFET). Although the on-current of JLNW-TFET decreases approximately ten times as much as that of the conventional TFET, its subthreshold swing is three times steeper than that of the conventional TFET and ambipolar current does not appear as a result of the structural characteristics.

Investigation of Corner Effect and Identification of Tunneling Regimes in L-Shaped Tunnel Field-Effect-Transistor.

Corner-effect existing in L-shaped tunnel field-effect-transistor (LTFET) was investigated using numerical simulations and band diagram analysis. It was found that the corner-effect is caused by the convergence of electric field in the sharp source corner present in an LTFET, thereby increasing the electric field in the sharp source corner region. It was found that in the corner-effect region tunneling starts early, as a function of applied bias, as compared to the rest of the channel not affected by corner-effect.

Work-Function Engineering of Source-Overlapped Dual-Gate Tunnel Field-Effect Transistor.

A source-overlapped dual-material gate TFET (SODM-TFET), which features different materials in its source-overlapped and channel gates, is proposed here, and its performance is investigated for various channel and source gate work functions (ψmc and ψms, respectively). Previous studies reported a hump effect in source-overlapped TFETs (SO-TFETs) and relatively high currents in the ambipolar state. The flat-band voltage in our SODM-TFET was controlled by modulating ψms and ψmc, allowing to reduce the hump effect and suppressing the ambipolar current.

Electrical Characteristics of Ge/Si-Based Source Pocket Tunnel Field-Effect Transistors.

Two types of Ge/Si-based novel tunnel field-effect transistors (TFETs) with source pockets are proposed. In the proposed Ge/Si-based TFETs, the materials in the source, channel, and drain are Ge, Si, and Si, respectively, and the gate shortly overlaps the source. One of the proposed TFETs has an intrinsic Ge pocket and the other has an intrinsic Si pocket, shallowly doped in the source region below the source-overlapped gate.

Metal oxide-graphene field-effect transistor: interface trap density extraction model.

A simple to implement model is presented to extract interface trap density of graphene field effect transistors. The presence of interface trap states detrimentally affects the device drain current-gate voltage relationship -. At the moment, there is no analytical method available to extract the interface trap distribution of metal-oxide-graphene field effect transistor (MOGFET) devices.

Analytic modeling of a depletion-mode cylindrical surrounding-gate nanowire field-effect transistor.

A compact model for depletion-mode p-type cylindrical surrounding-gate nanowire field-effect transistors (SGNWFETs) is proposed. The SGNWFET model consists of two back-to-back Schottky diodes for the metal-semiconductor (MS) contacts and the intrinsic SGNWFET. Based on the electrostatic method, the intrinsic SGNWFET model was derived from current conduction mechanisms attributed to bulk charges through the center neutral region, in addition to accumulation charges through the surface accumulation region.

Dependences of the electrical properties on the diameter and the doping concentration of the Si nanowire field effect transistors with a Schottky metal-semiconductor contact.

A compact model of the current-voltage (I-V) characteristics for the Si nanowire field effect transistor (FET) taking into account dependence of the analytical electrical properties on the diameter and the concentration of the Si nanowire of the FETs with a Schottky metal-semiconductor contact has been proposed. I-V characteristics of the nanowire FETs were analytically calculated by using a quantum drift-diffusion current transport model taking into account an equivalent circuit together with the quantum effect of the Si nanowires and a Schottky model at Schottky barriers. The material parameters dependent on different diameters and concentrations of the Si nanowire were numerically estimated from the physical properties of the Si nanowire.

Explicit continuous current-voltage (I-V) models for fully-depleted surrounding-gate MOSFETs (SGMOSFETs) with a finite doping body.

An analytical and continuous dc model for cylindrical doped surrounding-gate MOSFETs (SGMOSFETs) in the fully-depleted regime is presented. Starting from Poisson's equation, an implicit charge equation is derived approximately by a superposition principle with the exact channel potential and the charge equations in the depletion approximation. Also, a new explicit charge equation is derived from the implicit charge equation.

Fabrication and characterization of a double quantum dot structure.

We report the fabrication and characterization of a new type of double quantum dot (QD) structure. We utilize standard CMOS processing steps without any modification to fabricate the double QD. We form three CMOS poly-Si gates with oxide sidewall spacers in series on a silicon-on-insulator nanowire.

Multi-valued logic circuits using hybrid circuit consisting of three gates single-electron transistors (TG-SETs) and MOSFETs.

New multi-valued logic (MVL) families using the hybrid circuits consisting of three gates single-electron transistors (TG-SETs) and a metal-oxide-semiconductor field-effect transistor (MOSFET) are proposed. The use of SETs offers periodic literal characteristics due to Coulomb oscillation of SET, which allows a realization of binary logic (BL) circuits as well as multi-valued logic (MVL) circuits. The basic operations of the proposed MVL families are successfully confirmed through SPICE circuit simulation based on the physical device model of a TG-SET.

New adders using hybrid circuit consisting of three-gate single-electron transistors (TG-SETs) and MOSFETs.

A half-adder (HA) and a full-adder (FA) using hybrid circuits combining three-gate single-electron transistors (TG-SETs) with metal-oxide-semiconductor field-effect-transistors (MOSFETs) are proposed. The proposed HA consists of three TG-SETs, two enhanced-mode NMOSFETs, and two depletion-mode NMOSFETs, and the proposed FA consists of eight TG-SETs, two enhanced-mode NMOSFETs, and two depletion-mode NMOSFETs. The complexities in the HA and the FA are 7 and 12, respectively, and the worst-case delays in the HA and the FA are 1.

Equivalent circuit model of semiconductor nanowire diode by SPICE.

An equivalent circuit model of nanowire diodes is introduced. Because nanowire diodes inevitably involve a metal-semiconductor-metal structure, they consist of two metal-semiconductor contacts and one resistor in between these contacts. Our equivalent circuit consists of two Schottky diodes and one resistor.