Nonideality in Arrayed Carbon Nanotube Field Effect Transistors Revealed by High-Resolution Transmission Electron Microscopy.

High density and high semiconducting-purity single-walled carbon nanotube array (A-CNT) have recently been demonstrated as promising candidates for high-performance nanoelectronics. Knowledge of the structures and arrangement of CNTs within the arrays and their interfaces to neighboring CNTs, metal contacts, and dielectrics, as the key components of an A-CNT field effect transistor (FET), is essential for device mechanistic understanding and further optimization, particularly considering that the current technologies for the fabrication of A-CNT wafers are mainly laboratory-level solution-based processes. Here, we conduct a systematic investigation into the microstructures of A-CNT FETs mainly via cross-sectional high-resolution transmission electron microscopy and tentatively establish a framework consisting of up to 11 parameters which can be used for structure-side quality evaluation of the A-CNT FETs.

Interface States in Gate Stack of Carbon Nanotube Array Transistors.

A deep understanding of the interface states in metal-oxide-semiconductor (MOS) structures is the premise of improving the gate stack quality, which sets the foundation for building field-effect transistors (FETs) with high performance and high reliability. Although MOSFETs built on aligned semiconducting carbon nanotube (A-CNT) arrays have been considered ideal energy-efficient successors to commercial silicon (Si) transistors, research on the interface states of A-CNT MOS devices, let alone their optimization, is lacking. Here, we fabricate MOS capacitors based on an A-CNT array with a well-designed layout and accurately measure the capacitance-voltage and conductance-voltage (C-V and G-V) data.