Simulation of a randomly percolated CNT network for an improved analog physical unclonable function.

Carbon nanotube networks (CNTs)-based devices are well suited for the physically unclonable function (PUF) due to the inherent randomness of the CNT network, but CNT networks can vary significantly during manufacturing due to various controllable process conditions, which have a significant impact on PUF performance. Therefore, optimization of process conditions is essential to have a PUF with excellent performance. However, because it is time-consuming and costly to fabricate directly under various conditions, we implement randomly formed CNT network using simulation and confirm the variable correlation of the CNT network optimized for PUF performance.

Gate Capacitance Coupling of Double-Gate Carbon Nanotube Network Transistors.

Carbon nanotube (CNT) network channels constructed using a high-purity CNT solution for use in CNT thin-film transistors have the advantages of the possibility of requiring a low-temperature process and needing no special equipment. However, there are empty spaces between individual CNTs, resulting in unexpected effects. In this study, double-gate (DG) CNT network transistors were fabricated and measured in four different configurations to observe the capacitive coupling effects between the top gate (TG) and bottom gate (BG) in the DG structure.

Wafer-scale striped network transistors based on purified semiconducting carbon nanotubes for commercialization.

Highly purified and solution-processed semiconducting carbon nanotubes (s-CNTs) have developed rapidly over the past several decades and are near-commercially available materials that can replace silicon due to its large-area substrate deposition and room-temperature processing compatibility. However, the more s-CNTs are purified, the better their electrical performance, but considerable effort and long centrifugation time are required, which can limit commercialization due to high manufacturing costs. In this work, we therefore fabricated 'striped' CNT network transistor across industry-standard 8 inch wafers.