We fabricated a thermoelectric device with a silicide/silicon laminated hetero-structure by using RF sputtering and rapid thermal annealing. The device was observed to have Ohmic characteristics by I-V measurement. The temperature differences and Seebeck coefficients of the proposed silicide/silicon laminated and bulk structure were measured.
View Article and Find Full Text PDFA silicon nanowire one-dimensional thermoelectric device is presented as a solution to enhance thermoelectric performance. A top-down process is adopted for the definition of 50 nm silicon nanowires (SiNWs) and the fabrication of the nano-structured thermoelectric devices on silicon on insulator (SOl) wafer. To measure the Seebeck coefficients of 50 nm width n- and p-type SiNWs, a thermoelectric test structure, containing SiNWs, micro-heaters and temperature sensors is fabricated.
View Article and Find Full Text PDFSilicon-based thermoelectric nanowires were fabricated by using complementary metal-oxide-semiconductor (CMOS) technology. 50 nm width n- and p-type silicon nanowires (SiNWs) were manufactured using a conventional photolithography method on 8 inch silicon wafer. For the evaluation of the Seebeck coefficients of the silicon nanowires, heater and temperature sensor embedded test patterns were fabricated.
View Article and Find Full Text PDFJ Nanosci Nanotechnol
April 2012
50 nm wide n-type silicon nanowires have been manufactured by using a top-down process in order to investigate the thermoelectric properties of silicon nanowire. Nanowire test structures with platinum heaters and temperature sensors were fabricated. The extracted temperature coefficient of resistance (TCR) of the temperature sensors was 786.
View Article and Find Full Text PDFIn this paper, n/p-type nickel-silicided Schottky diodes were fabricated by incorporating antimony atoms near the nickel silicide/Si junction interface and the electrical characteristics were studied through measurements and simulations. The effective Schottky barrier height (SBH) for electron, extracted from the thermionic emission model, drastically decreased from 0.68 to less than 0.
View Article and Find Full Text PDFSilicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured.
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