Ferroelectric Stochasticity in 2D CuInPS and Its Application for True Random Number Generator.

True random number generators (TRNGs), which create cryptographically secure random bitstreams, hold great promise in addressing security concerns regarding hardware, communication, and authentication in the Internet of Things (IoT) realm. Recently, TRNGs based on nanoscale materials have gained considerable attention for avoiding conventional and predictable hardware circuitry designs that can be vulnerable to machine learning (ML) attacks. In this article, a low-power and low-cost TRNG developed by exploiting stochastic ferroelectric polarization switching in 2D ferroelectric CuInPS (CIPS)-based capacitive structures, is reported.

The 3D Monolithically Integrated Hardware Based Neural System with Enhanced Memory Window of the Volatile and Non-Volatile Devices.

3D neuromorphic hardware system is first demonstrated in neuromorphic application as on-chip level by integrating array devices with CMOS circuits after wafer bonding (WB) and interconnection process. The memory window of synaptic device is degraded after WB and 3 Dimesional (3D) integration due to process defects and thermal stress. To address this degradation, Ag diffusion in materials of TaO and HfO is studied in a volatile memristor, furthermore, the interconnection and gate metal Ru are investigated to reduce defective traps of gate interface in non-volatile memory devices.

CMOS-Integrated Ternary Content Addressable Memory using Nanocavity CBRAMs for High Sensing Margin.

The development of data-intensive computing methods imposes a significant load on the hardware, requiring progress toward a memory-centric paradigm. Within this context, ternary content-addressable memory (TCAM) can become an essential platform for high-speed in-memory matching applications of large data vectors. Compared to traditional static random-access memory (SRAM) designs, TCAM technology using non-volatile resistive memories (RRAMs) in two-transistor-two-resistor (2T2R) configurations presents a cost-efficient alternative.

Artificial Visual Systems Fabricated with Ferroelectric van der Waals Heterostructure for In-Memory Computing Applications.

Rapid developments in artificial neural network techniques and retina-inspired artificial visual systems are required to realize the sensing, processing, and memorization of an optical signal in a single device. Herein, a ferroelectric field-effect transistor fabricated with CuInPS and α-InSe van der Waals heterostructures is proposed and demonstrated for the development of an artificial visual system. The dipole polarizations are coupled and bidirectionally locked inside the ferroelectric α-InSe along the in-plane and out-of-plane directions and are controlled by the gate voltages.

Dual Piezoelectric Energy Investing and Harvesting Interface for High-Voltage Input.

A novel harvesting interface for multiple piezoelectric transducers (PZTs) is proposed for high-voltage energy harvesting. Pre-biasing a PZT prior to its mechanical deformation increases its damping force, resulting in higher energy extraction. Unlike the conventional harvesters where a PZT-generated output is assumed to be continuous sinusoidal and output polarity is assumed to be alternating every cycle, PZT-generated output from human motion is expected to be random.

Biologically Plausible Artificial Synaptic Array: Replicating Ebbinghaus' Memory Curve with Selective Attention.

The nature of repetitive learning and oblivion of memory enables humans to effectively manage vast amounts of memory by prioritizing information for long-term storage. Inspired by the memorization process of the human brain, an artificial synaptic array is presented, which mimics the biological memorization process by replicating Ebbinghaus' forgetting curve. To construct the artificial synaptic array, signal-transmitting access transistors and artificial synaptic memory transistors are designed using indium-gallium-zinc-oxide and poly(3-hexylthiophene), respectively.

A multiple negative differential resistance heterojunction device and its circuit application to ternary static random access memory.

For increasing the restricted bit-density in the conventional binary logic system, extensive research efforts have been directed toward implementing single devices with a two threshold voltage (VTH) characteristic via the single negative differential resistance (NDR) phenomenon. In particular, recent advances in forming van der Waals (vdW) heterostructures with two-dimensional crystals have opened up new possibilities for realizing such NDR-based tunneling devices. However, it has been challenging to exhibit three VTH through the multiple-NDR (m-NDR) phenomenon in a single device even by using vdW heterostructures.

Functionalized Organic Material Platform for Realization of Ternary Logic Circuit.

Negative differential resistance/transconductance (NDR/NDT) has been attracting significant attention as a key functionality in the development of multivalued logic (MVL) systems that can overcome the limits of conventional binary logic devices. A high peak-to-valley current ratio (PVCR) and more than double-peak transfer characteristics are required to achieve a stable MVL operation. In this study, an organic NDR (ONDR) device with double-peak transfer characteristics and a high peak-to-valley current ratio (PVCR; >10) is fabricated by utilizing an organic material platform for the development of a key element device for MVL applications.

A High-Voltage Energy-Harvesting Interface for Irregular Kinetic Energy Harvesting in IoT Systems with 1365% Improvement Using All-NMOS Power Switches and Ultra-low Quiescent Current Controller.

An energy-harvesting interface for kinetic energy harvesting from high-voltage piezoelectric and triboelectric generators is proposed in this paper. Unlike the conventional kinetic energy-harvesting interfaces optimized for continuous sinusoidal input, the proposed harvesting interface can efficiently handle irregular and random high voltage energy inputs. An N-type mosfet (NMOS)-only power stage design is introduced to simplify power switch drivers and minimize conduction loss.

Remote Gating of Schottky Barrier for Transistors and Their Vertical Integration.

This paper introduces a strategy to modulate a Schottky barrier formed at a graphene-semiconductor heterojunction. The modulation is performed by controlling the work function of graphene from a gate that is placed laterally away from the graphene-semiconductor junction, which we refer to as the remote gating of a Schottky barrier. The remote gating relies on the sensitive work function of graphene, whose local variation induced by locally applied field effect affects the change in the work function of the entire material.

A 10.6mm Fully-Integrated, Wireless Sensor Node with 8GHz UWB Transmitter.

This paper presents a complete, autonomous, wireless temperature sensor, fully encapsulated in a 10.6mm volume. The sensor includes solar energy harvesting with an integrated 2 μAh battery, optical receiver for programming, microcontroller and memory, 8GHz UWB transmitter, and miniaturized custom antennas with a wireless range of 7 meters.

MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems.

As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized-yet reusable-components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead.