Temperature-Dependent Opacity of the Gate Field Inside MoS Field-Effect Transistors.

The transport behaviors of MoS field-effect transistors (FETs) with various channel thicknesses are studied. In a 12 nm thick MoS FET, a typical switching behavior is observed with an / ratio of 10. However, in 70 nm thick MoS FETs, the gating effect weakens with a large off-current, resulting from the screening of the gate field by the carriers formed through the ionization of S vacancies at 300 K.

Coulomb scattering mechanism transition in 2D layered MoTe: effect of high-κ passivation and Schottky barrier height.

Clean interface and low contact resistance are crucial requirements in two-dimensional (2D) materials to preserve their intrinsic carrier mobility. However, atomically thin 2D materials are sensitive to undesired Coulomb scatterers such as surface/interface adsorbates, metal-to-semiconductor Schottky barrier (SB), and ionic charges in the gate oxides, which often limits the understanding of the charge scattering mechanism in 2D electronic systems. Here, we present the effects of hafnium dioxide (HfO) high-κ passivation and SB height on the low-frequency (LF) noise characteristics of multilayer molybdenum ditelluride (MoTe) transistors.

Electrothermal Local Annealing via Graphite Joule Heating on Two-Dimensional Layered Transistors.

A simple but powerful device platform for electrothermal local annealing (ELA) via graphite Joule heating on the surface of transition-metal dichalcogenide, is suggested here to sustainably restore intrinsic electrical properties of atomically thin layered materials. Such two-dimensional materials are easily deteriorated by undesirable surface/interface adsorbates and are screened by a high metal-to-semiconductor contact resistance. The proposed ELA allows one to expect a better electrical performance such as an excess electron doping, an enhanced carrier mobility, and a reduced surface traps in a monolayer molybdenum disulfide (MoS)/graphite heterostructure.

Suppression of Interfacial Current Fluctuation in MoTe2 Transistors with Different Dielectrics.

For transition metal dichalcogenides, the fluctuation of the channel current due to charged impurities is attributed to a large surface area and a thickness of a few nanometers. To investigate current variance at the interface of transistors, we obtain the low-frequency (LF) noise features of MoTe2 multilayer field-effect transistors with different dielectric environments. The LF noise properties are analyzed using the combined carrier mobility and carrier number fluctuation model which is additionally parametrized with an interfacial Coulomb-scattering parameter (α) that varies as a function of the accumulated carrier density (Nacc) and the location of the active channel layer of MoTe2.

Voltage Scaling of Graphene Device on SrTiO3 Epitaxial Thin Film.

Electrical transport in monolayer graphene on SrTiO3 (STO) thin film is examined in order to promote gate-voltage scaling using a high-k dielectric material. The atomically flat surface of thin STO layer epitaxially grown on Nb-doped STO single-crystal substrate offers good adhesion between the high-k film and graphene, resulting in nonhysteretic conductance as a function of gate voltage at all temperatures down to 2 K. The two-terminal conductance quantization under magnetic fields corresponding to quantum Hall states survives up to 200 K at a magnetic field of 14 T.

Ferroelectric Single-Crystal Gated Graphene/Hexagonal-BN/Ferroelectric Field-Effect Transistor.

The effect of a ferroelectric polarization field on the charge transport in a two-dimensional (2D) material was examined using a graphene monolayer on a hexagonal boron nitride (hBN) field-effect transistor (FET) fabricated using a ferroelectric single-crystal substrate, (1-x)[Pb(Mg1/3Nb2/3)O3]-x[PbTiO3] (PMN-PT). In this configuration, the intrinsic properties of graphene were preserved with the use of an hBN flake, and the influence of the polarization field from PMN-PT could be distinguished. During a wide-range gate-voltage (VG) sweep, a sharp inversion of the spontaneous polarization affected the graphene channel conductance asymmetrically as well as an antihysteretic behavior.

Quantum Hall conductance of graphene combined with charge-trap memory operation.

The combination of quantum Hall conductance and charge-trap memory operation was qualitatively examined using a graphene field-effect transistor. The characteristics of two terminal quantum Hall conductance appeared clearly on the background of a huge conductance hysteresis during a gate-voltage sweep for a device using monolayer graphene as a channel,hexagonal boron-nitride flakes as a tunneling dielectric and defective silicon oxide as the charge storage node. Even though there was a giant shift of the charge neutrality point, the deviation of quantized resistance value at the state of filling factor 2 was less than 1.