We demonstrated the feasibility of metal and dielectric liners using a solution process for deep trench capacitor application. The deep Si trench via with size of 10.3 microm and depth of 71 microm were fabricated by Bosch process in deep reactive ion etch (DRIE) system.
View Article and Find Full Text PDFWe used micro contact printing (micro-CP) to fabricate inverted coplanar pentacene thin film transistors (TFTs) with 1-microm channels. The patterning of micro-scale source/drain electrodes without etch process was successfully achieved using Polydimethylsiloxane (PDMS) elastomer stamp. We used the Ag nano particle ink as an electrode material, and the sheet resistance and surface roughness of the Ag electrodes were effectively reduced with the 2-step thermal annealing on a hotplate, which improved the mobility, the on-off ratio, and the subthreshold slope (SS) of the pentacene TFTs.
View Article and Find Full Text PDFWe designed and fabricated a bimorph cantilever array for sustainable power with an integrated Cu proof mass to obtain additional power and current. We fabricated a cantilever system using single-crystal piezoelectric material and compared the calculations for single and arrayed cantilevers to those obtained experimentally. The vibration energy harvester had resonant frequencies of 60.
View Article and Find Full Text PDFWe have fabricated the flexible pentacene based organic thin film transistors (OTFTs) with formulated poly[4-vinylphenol] (PVP) gate dielectrics treated by CF4/O2 plasma on poly[ethersulfones] (PES) substrate. The solution of gate dielectrics is made by adding methylated poly[melamine-co-formaldehyde] (MMF) to PVP. The PVP gate dielectric layer was cross linked at 90 degrees under UV ozone exposure.
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