Implementation of field-programmable Gate array-based clock synchronization in the fiber channel communication system.

A sub-nanosecond clock synchronization scheme based on the field programmable gate array (FPGA) is proposed for the Fiber Channel (FC) communication system in this paper. The counter value of the slave node is synchronized to that of the master node through the embedded IEEE 1588 protocol over the communication link. In order to ensure the counter clocks have the same frequency in both nodes, which is recovered from the FC communication link, the clock phase difference is measured by the digital dual mixer time difference technique and the data recovery technique in the Gigabyte Transceiver, and then it is compensated by the mixed-mode clock manager in FPGAs.

Time-interleaved system mismatch estimation based on correlation function and particle swarm optimization algorithm.

The time-interleaved analog-to-digital converters (TIADCs) technique is an efficient solution to improve the sampling rate of the acquisition system with low-speed ADCs. However, channel mismatches such as gain mismatch, time skew mismatch, and offset mismatch may seriously degrade the performance of TIADC. Furthermore, for high-speed signal acquisition, the gain and time skew mismatches would vary with the signal frequency, and the traditional fixed model does not work any longer.

Statistical neural network (SNN) for predicting signal-to-noise ratio (SNR) from static parameters and its validation in 16-bit, 125-MSPS analog-to-digital converters (ADCs).

In the analog-to-digital converter (ADC) test process, the static and dynamic performance parameters are the most important, and the tests for these parameters account for the bulk of the ADC test cost. These two types of parameters follow certain relationships, which are incorporated into the ADC test to reduce the cost. In this paper, we focus on the signal-to-noise ratio (SNR), a key indicator of the dynamic performances of ADCs.

Multiband sparse signal reconstruction through direct one-bit sampling.

Compressive sensing (CS) aims at decreasing sampling rate to reduce the needed number of samples. On the other hand, the one-bit CS is proposed to reduce the quantization bit. In this paper, we proposed a one-bit CS system aiming at acquiring the multiband sparse signal which is a very popular signal model in wireless communication, especially in cognitive radio.

GHz sampling hardware implementation with sub-Nyquist coprime sampling rates.

A sub-Nyquist coprime sampling system for sparse signals is implemented in this article. The proposed system is composed of coprime sampling hardware and a multicoset signal reconstruction algorithm. A pair of uniform samplers is utilized in the hardware to sample a wideband spare analog signal with an uncertain difference in start times.

Sequential time interleaved random equivalent sampling for repetitive signal.

Compressed sensing (CS) based sampling techniques exhibit many advantages over other existing approaches for sparse signal spectrum sensing; they are also incorporated into non-uniform sampling signal reconstruction to improve the efficiency, such as random equivalent sampling (RES). However, in CS based RES, only one sample of each acquisition is considered in the signal reconstruction stage, and it will result in more acquisition runs and longer sampling time. In this paper, a sampling sequence is taken in each RES acquisition run, and the corresponding block measurement matrix is constructed using a Whittaker-Shannon interpolation formula.