A 2.3-ps RMS Resolution Time-to-Digital Converter Implemented in a Low-Cost Cyclone V FPGA.

We present a nonuniform multiphase (NUMP) method to construct a high-resolution time-to-digital converter (TDC) for low-cost field-programmable gate array (FPGA) devices. The NUMP method involves a system clock being passed through a series of delay elements to generate multiple clocks with different phase shifts. The phases of the rising and falling edges of all the clocks are sorted in order and the states of all the clocks are latched when a hit signal arrives.