ACS Appl Mater Interfaces
December 2024
A machine learning (ML) strategy is suggested to optimize dual-layer oxide thin film transistor (TFTs) performance. In this study, Bayesian optimization (BO), an algorithm recognized for its efficiency in optimizing material design, is applied to guide the design of a channel layer composed of IZO and IGZO. The sputtering fabrication process, which has attracted attention as an oxide semiconductor channel layer deposition method, is fine-tuned using ML to enhance multiple electrical characteristics of transistors: field-effect mobility, threshold voltage, and subthreshold swing.
View Article and Find Full Text PDFMultivalued logic (MVL) technology is a promising solution for improving data density and reducing power consumption in comparison to complementary metal-oxide-semiconductor (CMOS) technology. Currently, heterojunction transistors (TRs) with negative differential transconductance (NDT) characteristics, which play an important role in the function of MVL circuits, adopt organic or 2D semiconductors as active layers, but it is still difficult to apply conventional CMOS processes. Herein, we demonstrate an oxide semiconductor (OS) heterojunction TR with NDT characteristics composed of p-type copper(I) oxide (CuO) and n-type indium gallium zinc oxide (IGZO) using the conventional CMOS manufacturing processes.
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