Single-photon avalanche diode fabricated in standard 55 nm bipolar-CMOS-DMOS technology with sub-20 V breakdown voltage.

This paper presents a single-photon avalanche diode (SPAD) in 55 nm bipolar-CMOS-DMOS (BCD) technology. In order to realize a SPAD having sub-20 V breakdown voltage for mobile applications while preventing high tunneling noise, a high-voltage N-well available in BCD is utilized to implement the avalanche multiplication region. The resulting SPAD has a breakdown voltage of 18.

Noise optimization of single-photon avalanche diodes fabricated in 110 nm CMOS image sensor technology.

This paper presents the effect of shallow trench isolation (STI) on the dark count rate (DCR) and after-pulsing probability (APP) of deep-junction-based single-photon avalanche diodes (SPADs). Two different SPADs were fabricated in 110 nm CMOS image sensor technology, one with STI and the other without STI between its anode and cathode. With TCAD simulations and measurements, we have clearly demonstrated that the SPAD without STI enables a dramatic decrease in DCR by more than three orders of magnitude without suffering from the lateral leakage current between the anode and cathode.