Design of a Capacitorless Dynamic Random Access Memory Based on Ultra-Thin Polycrystalline Silicon Junctionless Field-Effect Transistor with Dual-Gate.

In this paper, a 1T-DRAM based on the junctionless field-effect transistor (JLFET) with an ultrathin polycrystalline silicon layer was designed and investigated by using technology computer-aided design simulation (TCAD). The application of a negative voltage at the control gate results in the generation of holes in the storage region by the band-to-band tunneling (BTBT) effect. Memory characteristics such as sensing margin and retention time are affected by the doping concentration of the storage region, bias condition of the program, and length of the intrinsic region.

Analysis of CMOS Logic Inverter Based on Gate-All-Around Field-Effect Transistors with the Strained-Silicon Layer for Improving the Switching Performances.

In this paper, we adopt the vertical core-shell nanowire field-effect transistors based on the Silicon-germanium (SiGe)/strained-silicon (strained-Si) layer as a method to improve the performance of the CMOS logic inverter by using technology computer aided design simulation. The lattice constant mismatch between the core region and the shell region causes the global strain of the Si region of the shell, which in turn changes the Si parameters. This phenomenon effects on the improvement the electrical characteristics in the -type MOSFET (MOSFET).

Analysis of Logic Inverter Based on Polycrystalline Silicon with Single Grain Boundary.

In this paper, we demonstrate the characteristics of a complementary metal-oxide-semiconductor (CMOS) logic inverter based on a polycrystalline-silicon (poly-Si) layer with a single grain boundary (GB). The proposed nanoscale CMOS logic inverter had been constructed on a poly-Si layer with a GB including four kind of traps at the center of the channel. The simulation variables are the acceptor-like deep trap (ADT), the donor-like deep trap (DDT), the acceptor-like shallow trap (AST) and the donor-like shallow trap (DST).

Design and Analysis of Metal-Oxide-Semiconductor Field-Effect Transistor-Based Capacitorless One-Transistor Embedded Dynamic Random-Access Memory with Double-Polysilicon Layer Using Grain Boundary for Hole Storage.

In this work, a capacitorless one-transistor embedded dynamic random-access memory based on a metal-oxide-semiconductor field-effect transistor with a double-polysilicon layer structure has been proposed and investigated using technology computer-aided design simulation. By using the grain boundary for hole storage, a higher sensing margin of 4.35 / is achieved compared to that without using the grain boundary.

Recessed-Gate GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistor Using a Dual Gate-Insulator Employing TiO₂/SiN.

In this work, we present a normally-off recessed-gate AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) using a TiO₂/SiN dual gate-insulator. We analyzed the electrical characteristics of the proposed device and found that the dual gate-insulator device achieves higher on-state currents than the device using a SiN gate-insulator because the high-k insulator layer of the dual gate-insulator improves the gate-controllability. The device using a TiO₂/SiN gate-insulator shows better gate leakage current characteristics than the device with only TiO₂ gate-insulator because of the high quality SiN gate-insulator.

Design and Optimization of Germanium-Based Gate-Metal-Core Vertical Nanowire Tunnel FET.

In this paper, a germanium-based gate-metal-core vertical nanowire tunnel field effect transistor (VNWTFET) has been designed and optimized using the technology computer-aided design (TCAD) simulation. In the proposed structure, by locating the gate-metal as a core of the nanowire, a more extensive band-to-band tunneling (BTBT) area can be achieved compared with the conventional core-shell VNWTFETs. The channel thickness (), the gate-metal height (), and the channel height () were considered as the design parameters for the optimization of device performances.

Simulation for Electrical Performances of the Capacitorless Dynamic Random Access Memory Based on Junctionless FinFETs.

This paper report a junctionless fin-type field-effect-transistor based capacitorless dynamic random access memory using three-dimensional technology computer-aided design simulations. The proposed 1T-DRAM is made up of a silicon germanium storage region surrounding a silicon fin. When the two materials form a heterojunction, a potential well is formed by the band discontinuity which carriers can be stored.

Effect of Interface Traps on the Device Performance of InGaAs-Based Gate-All-Around Tunneling Field-Effect Transistors.

The effect of interface traps on InGaAs-based vertical gate-all-around (GAA) tunneling field-effect transistors (TFETs) has been investigated using technology computer-aided design (TCAD) simulation. The interface traps distributed within different energy levels () in the energy bandgap of a semiconductor material exhibit various influences on the device performances. In this work, InGaAs-based TFETs are simulated to analyze the effects on the on-state current (), off-state current (), threshold voltage (), subthreshold swing (), and the ambipolar characteristics according to and type of the interface traps.

Analysis of Electrical Characteristics of InAlGaN/GaN-Based High Electron Mobility Transistors with AlGaN Back Barriers.

In this study, the effect of an AlGaN back-barrier on the electrical characteristics of InAlGaN/GaN high electron mobility transistors (HEMTs) was investigated. The dependence of the thickness and the Al composition of the AlGaN back-barrier on the off-state current (I) of the devices was investigated. An InAlGaN/GaN HEMT with an AlGaN back-barrier of thickness 20 nm exhibited lower because of the carrier confinement effect, which was caused by the back-barrier.