0.35 μm CMOS avalanche photodiode with high responsivity and responsivity-bandwidth product.

A highly sensitive avalanche photodiode (APD) in 0.35 μm CMOS technology is presented. Due to a thick intrinsic absorption layer, a high responsivity at a low bias voltage, where the avalanche gain is 1, is combined with an excellent avalanche gain at high voltages to achieve a maximum overall responsivity of the APD of more than 10 kA/W.

High-speed bipolar phototransistors in a 180 nm CMOS process.

Several high-speed pnp phototransistors built in a standard 180 nm CMOS process are presented. The phototransistors were implemented in sizes of 40×40 μm and 100×100 μm. Different base and emitter areas lead to different characteristics of the phototransistors.

PNP PIN bipolar phototransistors for high-speed applications built in a 180 nm CMOS process.

This work reports on three speed optimized pnp bipolar phototransistors build in a standard 180 nm CMOS process using a special starting wafer. The starting wafer consists of a low doped p epitaxial layer on top of the p substrate. This low doped p epitaxial layer leads to a thick space-charge region between base and collector and thus to a high -3 dB bandwidth at low collector-emitter voltages.