Ion Drift and Polarization in Thin SiO and HfO Layers Inserted in Silicon on Sapphire.

To reduce the built-in positive charge value at the silicon-on-sapphire (SOS) phase border obtained by bonding and a hydrogen transfer, thermal silicon oxide (SiO) layers with a thickness of 50-310 nm and HfO layers with a thickness of 20 nm were inserted between silicon and sapphire by plasma-enhanced atomic layer deposition (PEALD). After high-temperature annealing at 1100 °C, these layers led to a hysteresis in the drain current-gate voltage curves and a field-induced switching of threshold voltage in the SOS pseudo-MOSFET. For the inserted SiO with a thickness of 310 nm, the transfer transistor characteristics measured in the temperature ranging from 25 to 300 °C demonstrated a triple increase in the hysteresis window with the increasing temperature.

Diode-Like Current Leakage and Ferroelectric Switching in Silicon SIS Structures with Hafnia-Alumina Nanolaminates.

Silicon semiconductor-insulator-semiconductor (SIS) structures with high-k dielectrics are a promising new material for photonic and CMOS integrations. The "diode-like" currents through the symmetric atomic layer deposited (ALD) HfO/AlO/HfO… nanolayers with a highest rectification coefficient 10 are observed and explained by the asymmetry of the upper and lower heterointerfaces formed by bonding and ALD processes. As a result, different spatial charge regions (SCRs) are formed on both insulator sides.