Development of a Charge-Multiplication CMOS Image Sensor Based on Capacitive Trench for Low-Light-Level Imaging.

This paper presents an electron multiplication charge coupled device (EMCCD) based on capacitive deep trench isolation (CDTI) and developed using complementary metal oxide semiconductor (CMOS) technology. The CDTI transfer register offers a charge transfer inefficiency lower than 10-4 and a low dark current o 0.11nA/cm2 at room temperature.

Evaluation of Microlenses, Color Filters, and Polarizing Filters in CIS for Space Applications.

For the last two decades, the CNES optoelectronics detection department and partners have evaluated space environment effects on a large panel of CMOS image sensors (CIS) from a wide range of commercial foundries and device providers. Many environmental tests have been realized in order to provide insights into detection chain degradation in modern CIS for space applications. CIS technology has drastically improved in the last decade, reaching very high performances in terms of quantum efficiency (QE) and spectral selectivity.

A new TCAD simulation method for direct CMOS electron detectors optimization.

A custom CMOS image sensor hardened by design is characterized in a transmission electron microscope, with the aim to extract basic parameters such as the quantum efficiency, the modulation transfer function and finally the detective quantum efficiency. In parallel, a new methodology based on the combination of Monte Carlo simulation of electron distributions and TCAD simulations is proposed and performed on the same detector, and for the first time the basic parameters of a direct CMOS electron detector are extracted thanks to the TCAD. The methodology is validated by means of the comparison between experimental and simulation results.

Design of a CMOS image sensor pixel with embedded polysilicon nano-grating for near-infrared imaging enhancement.

Complementary metal-oxide semiconductor (CMOS) image sensor sensitivity in the near-infrared spectrum is limited by the absorption length in silicon. To deal with that limitation, we evaluate the implementation of a polysilicon nano-grating inside a pixel, at the transistor gate level of a 90 nm standard CMOS process, through opto-electrical simulations. The studied pixel structure involves a polysilicon nano-grating, designed with the fabrication layer of the transistor gate, which does not require any modifications in the process flow.