Experimental-Modeling Framework for Identifying Defects Responsible for Reliability Issues in 2D FETs.

In this work, a self-consistent method is used to identify and describe defects plaguing 300 mm integrated 2D field-effect transistors. This method requires measurements of the transfer characteristic hysteresis combined with physics-based modeling of charge carrier capture and emission processes using technology computer aided design (TCAD) tools. The interconnection of experiments and simulations allows one to thoroughly characterize charge trapping/detrapping by/from defects, depending on their energy position.

Challenges of Wafer-Scale Integration of 2D Semiconductors for High-Performance Transistor Circuits.

Large-area 2D-material-based devices may find applications as sensor or photonics devices or can be incorporated in the back end of line (BEOL) to provide additional functionality. The introduction of highly scaled 2D-based circuits for high-performance logic applications in production is projected to be implemented after the Si-sheet-based CFET devices. Here, a view on the requirements needed for full wafer integration of aggressively scaled 2D-based logic circuits, the status of developments, and the definition of the gaps to be bridged is provided.