Bottom-up fabrication of InAs-on-nothing MOSFET using selective area molecular beam epitaxy.

In this paper we report on the fabrication and electrical characterization of InAs-on-nothing metal-oxide-semiconductor field-effect transistor composed of a suspended InAs channel and raised InAs n+ contacts. This architecture is obtained using 3D selective and localized molecular beam epitaxy on a lattice mismatched InP substrate. The suspended InAs channel and InAs n+ contacts feature a reproducible and uniform shape with well-defined 3D sidewalls.

100 nm AlSb/InAs HEMT for ultra-low-power consumption, low-noise applications.

We report on high frequency (HF) and noise performances of AlSb/InAs high electron mobility transistor (HEMT) with 100 nm gate length at room temperature in low-power regime. Extrinsic cut-off frequencies fT/f max of 100/125 GHz together with minimum noise figure NF(min) = 0.5 dB and associated gain G(ass) = 12 dB at 12 GHz have been obtained at drain bias of only 80 mV, corresponding to 4 mW/mm DC power dissipation.

Gate length variation effect on performance of gate-first self-aligned In₀.₅₃Ga₀.₄₇As MOSFET.

A multi-gate n-type In₀.₅₃Ga₀.₄₇As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology.

Numerical and experimental assessment of charge control in III-V nano-metal-oxide-semiconductor field-effect transistor.

III-V Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) with a gate stack based on high-kappa dielectric appears as an appealing solution to increase the performance of either microwave or logic circuits with low supply voltage (V(DD)). The main objective of this work is to provide a theoretical model of the gate charge control in III-V MOS capacitors (MOSCAPs) using the accurate self-consistent solution of 1D and 2D Poisson-Schrödinger equations. This study allows us to identify the major mechanisms which must be included to get theoretical calculations in good agreement with experiments.