SHIP: a computational framework for simulating and validating novel technologies in hardware spiking neural networks.

Investigations in the field of spiking neural networks (SNNs) encompass diverse, yet overlapping, scientific disciplines. Examples range from purely neuroscientific investigations, researches on computational aspects of neuroscience, or applicative-oriented studies aiming to improve SNNs performance or to develop artificial hardware counterparts. However, the simulation of SNNs is a complex task that can not be adequately addressed with a single platform applicable to all scenarios.

Improving HfO-Based Resistive Switching Devices by Inserting a TaO Thin Film via Engineered In Situ Oxidation.

Resistive switching (RS) devices with binary and analogue operation are expected to play a key role in the hardware implementation of artificial neural networks. However, state of the art RS devices based on binary oxides (e.g.

Non-linear Memristive Synaptic Dynamics for Efficient Unsupervised Learning in Spiking Neural Networks.

Spiking neural networks (SNNs) are a computational tool in which the information is coded into spikes, as in some parts of the brain, differently from conventional neural networks (NNs) that compute over real-numbers. Therefore, SNNs can implement intelligent information extraction in real-time at the edge of data acquisition and correspond to a complementary solution to conventional NNs working for cloud-computing. Both NN classes face hardware constraints due to limited computing parallelism and separation of logic and memory.

Stimulated Ionic Telegraph Noise in Filamentary Memristive Devices.

Random telegraph noise is a widely investigated phenomenon affecting the reliability of the reading operation of the class of memristive devices whose operation relies on formation and dissolution of conductive filaments. The trap and the release of electrons into and from defects surrounding the filament produce current fluctuations at low read voltages. In this work, telegraphic resistance variations are intentionally stimulated through pulse trains in HfO-based memristive devices.

Evidence of soft bound behaviour in analogue memristive devices for neuromorphic computing.

The development of devices that can modulate their conductance under the application of electrical stimuli constitutes a fundamental step towards the realization of synaptic connectivity in neural networks. Optimization of synaptic functionality requires the understanding of the analogue conductance update under different programming conditions. Moreover, properties of physical devices such as bounded conductance values and state-dependent modulation should be considered as they affect storage capacity and performance of the network.

Role of Al doping in the filament disruption in HfO resistance switches.

Resistance switching devices, whose operation is driven by formation (SET) and dissolution (RESET) of conductive paths shorting and disconnecting the two metal electrodes, have recently received great attention and a deep general comprehension of their operation has been achieved. However, the link between switching characteristics and material properties is still quite weak. In particular, doping of the switching oxide layer has often been investigated only for looking at performance upgrade and rarely for a meticulous investigation of the switching mechanism.

Analog Memristive Synapse in Spiking Networks Implementing Unsupervised Learning.

Emerging brain-inspired architectures call for devices that can emulate the functionality of biological synapses in order to implement new efficient computational schemes able to solve ill-posed problems. Various devices and solutions are still under investigation and, in this respect, a challenge is opened to the researchers in the field. Indeed, the optimal candidate is a device able to reproduce the complete functionality of a synapse, i.

Resistive switching in high-density nanodevices fabricated by block copolymer self-assembly.

Bipolar resistive switching memories based on metal oxides offer a great potential in terms of simple process integration, memory performance, and scalability. In view of ultrahigh density memory applications, a reduced device size is not the only requirement, as the distance between different devices is a key parameter. By exploiting a bottom-up fabrication approach based on block copolymer self-assembling, we obtained the parallel production of bilayer Pt/Ti top electrodes arranged in periodic arrays over the HfO2/TiN surface, building memory devices with a diameter of 28 nm and a density of 5 × 10(10) devices/cm(2).

Engineered fabrication of ordered arrays of Au-NiO-Au nanowires.

In the present paper, a novel method to fabricate ordered arrays of Au/NiO/Au nanowires is described, with the aim of filling the gap between the fundamental study of the electrical properties of scattered single nanowires and the engineered fabrication of nanowire arrays. This approach mainly consists of the following steps: (a) electrodeposition of Au/Ni/Au nanowires into an ordered porous anodic aluminum oxide template; (b) mechanical polishing of the sample to expose the gold tips of Au/Ni/Au nanowires to the template surface; (c) in situ annealing of the Au/Ni/Au nanowires without removing the template. The resulting structure consists in an ordered array of Au/NiO/Au nanowires slightly protruding out of a flat aluminum oxide template.