Wafer-scale growth of single-crystal monolayer graphene on reusable hydrogen-terminated germanium.

The uniform growth of single-crystal graphene over wafer-scale areas remains a challenge in the commercial-level manufacturability of various electronic, photonic, mechanical, and other devices based on graphene. Here, we describe wafer-scale growth of wrinkle-free single-crystal monolayer graphene on silicon wafer using a hydrogen-terminated germanium buffer layer. The anisotropic twofold symmetry of the germanium (110) surface allowed unidirectional alignment of multiple seeds, which were merged to uniform single-crystal graphene with predefined orientation.

Reliability enhancement of germanium nanowires using graphene as a protective layer: aspect of thermal stability.

We synthesized thermally stable graphene-covered Ge (Ge@G) nanowires and applied them in field emission devices. Vertically aligned Ge@G nanowires were prepared by sequential growth of the Ge nanowires and graphene shells in a single chamber. As a result of the thermal treatment experiments, Ge@G nanowires were much more stable than pure Ge nanowires, maintaining their shape at high temperatures up to 850 °C.

Large-scale fabrication of 2-D nanoporous graphene using a thin anodic aluminum oxide etching mask.

A large-scale nanoporous graphene (NPG) fabrication method via a thin anodic aluminum oxide (AAO) etching mask is presented in this paper. A thin AAO film is successfully transferred onto a hydrophobic graphene surface under no external force. The AAO film is completely stacked on the graphene due to the van der Waals force.

A facile route to Si nanowire gate-all-around field effect transistors with a steep subthreshold slope.

We present a facile CMOS-compatible fabrication of lateral gate-all-around (GAA) field effect transistors (FETs) based on concentric Si-SiO₂/N(++)Si core-multi-shell nanowires (NWs). Si-SiO₂/N(++)Si core-multi-shell NWs were prepared by sequential Si NW growth, thermal oxidation and Si deposition processes in a single chamber. The GAA NW FET was then fabricated using the Si core, SiO₂ inner-shell, N(++) Si outer-shell as a channel, gate dielectric, and gate electrode, respectively.