A Feasible Alternative to FDSOI and FinFET: Optimization of W/LaO/Si Planar PMOS with 14 nm Gate-Length.

At the 90-nm node, the rate of transistor miniaturization slows down due to challenges in overcoming the increased leakage current (). The invention of high-k/metal gate technology at the 45-nm technology node was an enormous step forward in extending Moore's Law. The need to satisfy performance requirements and to overcome the limitations of planar bulk transistor to scales below 22 nm led to the development of fully depleted silicon-on-insulator (FDSOI) and fin field-effect transistor (FinFET) technologies.