Characterization of Lateral Structure of the Diode for Thin-Film Silicon Solar Cell.

The lateral structure of the p-i-n diode was characterized for thin-film silicon solar cell application. The structure can benefit from a wide intrinsic layer, which can improve efficiency without increasing cell thickness. Compared with conventional thin-film p-i-n cells, the p-i-n diode lateral structure exploited direct light irradiation on the absorber layer, one-side contact, and bifacial irradiation.

Effects of Electrode Thickness on Three-Dimensional NiCrAl Metal Foam Cathode for Lithium Ion Battery.

LiFePO4 electrodes using three dimensional NiCrAl alloy metal foam of different electrode thickness are prepared. In order to improve the electrochemical and cycle-life performance of lithium ion batteries, it is important to optimize the electrode thickness and mass loading of active material. As compared to those with thick electrode, the cells with thin electrode exhibit high rate performance and cycle-life behavior, due to the shorter diffusion length of lithium-ion and improved kinetic behavior.

50-nm Nano-Scaled Vertical-Transistor with NiSi₂ Seed-Induced Vertically Crystallized Poly-Silicon Channel for Very-Large-Scale-Integration.

Vertical-channel MOSFETs are hard to demonstrate a high electrical performance than the planar MOSFETs because of its polycrystalline-silicon (poly-Si) channel for 3-D CMOS ICs. In this paper, we have demonstrated a vertical poly-silicon-channel (VPSC) transistor NiSi2 seed-induced vertical crystallization (SIVC) and compared with the typical SG-VPC MOSFETs with solid-phase crystallization (SPC). The SIVC poly-Si showed large longitudinal grains with low defect trap sites, while the SPC poly-Si showed small spherical grains with large defect trap sites.

Sub-kT/q Subthreshold-Slope Using Negative Capacitance in Low-Temperature Polycrystalline-Silicon Thin-Film Transistor.

Realizing a low-temperature polycrystalline-silicon (LTPS) thin-film transistor (TFT) with sub-kT/q subthreshold slope (SS) is significantly important to the development of next generation active-matrix organic-light emitting diode displays. This is the first time a sub-kT/q SS (31.44 mV/dec) incorporated with a LTPS-TFT with polycrystalline-Pb(Zr,Ti)O3 (PZT)/ZrTiO4 (ZTO) gate dielectrics has been demonstrated.

Integrating Epitaxial-Like Pb(Zr,Ti)O3 Thin-Film into Silicon for Next-Generation Ferroelectric Field-Effect Transistor.

The development of ferroelectric random-access memory (FeRAM) technology with control of grain boundaries would result in a breakthrough for new nonvolatile memory devices. The excellent piezoelectric and electrical properties of bulk ferroelectrics are degraded when the ferroelectric is processed into thin films because the grain boundaries then form randomly. Controlling the nature of nucleation and growth are the keys to achieving a good crystalline thin-film.

Leakage current behavior of the bottom gate poly thin-film transistor fabricated by copper damascene process.

Bottom-gated polycrystalline-silicon (poly-Si) thin-film transistors (TFT's) with a planarized copper (Cu) gate for large-area displays have been fabricated and characterized. The 500 nm depth of trenchs are filled up with 400 nm, 500 nm, 600 nm thickness of Cu using the damascene process of VLSI technology, poly-Si TFT's with 100 nm thick gate insulator are fabricated on the Cu gate. As the Cu gate's thickness becomes thinner, the anomalous leakage current of poly-Si TFT's is reduced significantly both before and after electrical stressing.

Electrical activation of ion mass doped phosphorous.

In this study, three different crystalline states of silicon were prepared to be doped with phosphorous by IMD, amorphous, poly crystalline and single crystalline silicon. The dose was controlled by IMD duration time and heat treatment for electrical activation was done in RTA and Furnace. In case of RTA, annealing temperature was controlled by the duration time of power application.

Charge retention characteristics of silicide-induced crystallized polycrystalline silicon floating gate thin-film transistors for active matrix organic light-emitting diode.

In this work, non-volatile memory thin-film transistor (NVM-TFT) was fabricated by nickel silicide-induced laterally crystallized (SILC) polycrystalline silicon (poly-Si) as the active layer. The nickel seed silicide-induced crystallized (SIC) poly-Si was used as storage layer which is embedded in the gate insulator. The novel unit pixel of active matrix organic light-emitting diode (AMOLED) using NVM-TFT is proposed and investigated the electrical and optical performance.

Tilted back exposure for lightly doped drain structure in metal induced lateral crystallization poly Si thin film transistors.

It has been known that LDD is essential to reduce the leakage current in poly TFTs, which has been regarded as one of the most important issues in poly TFT characteristics. However, according to the conventional process, an extra mask is needed solely for the LDD formation, which is not only complicated but also difficult to maintain the reproducibility. In this work, a simple method has been introduced for formation of LDD structure in poly Si TFTs, Tilted Back Exposure (TBE) technique.

Electrical stress effect on on-current of MILC poly-Si thin-film transistors.

In this study, we studied the effect of the electrical stress on the on-current of metal-induced laterally crystallized poly-Si TFTs. It was found that the electrical performance of polycrystalline silicon thin-film transistors (TFTs) is greatly affected by the electrical stress. Under the electrical stress condition, the drain current increases due to hot-electron trap at the drain junction.

Electrical stress effect on the leakage current of metal-induced laterally crystallized p-channel poly-Si TFTs.

A p-type polycrystalline silicon thin-film transistor (TFT) was fabricated using the metal-induced lateral crystallization (MILC) technique at 550 degrees C. To reduce the leakage current in the MILC TFT, electrical stress (ES), newly developed in this work, was applied prior to the I(D)-V(G) measurements. It was found that ES is effective only when the TFT is under off-state.

Effect of lightly doped drain structure on P-channel metal induced lateral crystallization thin film transistors.

A Lightly Doped Drain (LDD) structure is known to be very effective in preventing hot electrons in modern NMOS transistors. In this work, the lightly doped region was formed in poly TFT by using a separate LDD mask aligned to a gate mask. The misalignment can be calculated to be about 1.