Leakage current behavior of the bottom gate poly thin-film transistor fabricated by copper damascene process.

Bottom-gated polycrystalline-silicon (poly-Si) thin-film transistors (TFT's) with a planarized copper (Cu) gate for large-area displays have been fabricated and characterized. The 500 nm depth of trenchs are filled up with 400 nm, 500 nm, 600 nm thickness of Cu using the damascene process of VLSI technology, poly-Si TFT's with 100 nm thick gate insulator are fabricated on the Cu gate. As the Cu gate's thickness becomes thinner, the anomalous leakage current of poly-Si TFT's is reduced significantly both before and after electrical stressing.

Electrical activation of ion mass doped phosphorous.

In this study, three different crystalline states of silicon were prepared to be doped with phosphorous by IMD, amorphous, poly crystalline and single crystalline silicon. The dose was controlled by IMD duration time and heat treatment for electrical activation was done in RTA and Furnace. In case of RTA, annealing temperature was controlled by the duration time of power application.

Charge retention characteristics of silicide-induced crystallized polycrystalline silicon floating gate thin-film transistors for active matrix organic light-emitting diode.

In this work, non-volatile memory thin-film transistor (NVM-TFT) was fabricated by nickel silicide-induced laterally crystallized (SILC) polycrystalline silicon (poly-Si) as the active layer. The nickel seed silicide-induced crystallized (SIC) poly-Si was used as storage layer which is embedded in the gate insulator. The novel unit pixel of active matrix organic light-emitting diode (AMOLED) using NVM-TFT is proposed and investigated the electrical and optical performance.

Electrical stress effect on the leakage current of metal-induced laterally crystallized p-channel poly-Si TFTs.

A p-type polycrystalline silicon thin-film transistor (TFT) was fabricated using the metal-induced lateral crystallization (MILC) technique at 550 degrees C. To reduce the leakage current in the MILC TFT, electrical stress (ES), newly developed in this work, was applied prior to the I(D)-V(G) measurements. It was found that ES is effective only when the TFT is under off-state.