Mapping of integrated PIN diodes with a 3D architecture by scanning microwave impedance microscopy and dynamic spectroscopy.

This work addresses the need for a comprehensive methodology for nanoscale electrical testing dedicated to the analysis of both "front end of line" (FEOL) (doped semiconducting layers) and "back end of line" (BEOL) layers (metallization, trench dielectric, and isolation) of highly integrated microelectronic devices. Based on atomic force microscopy, an electromagnetically shielded and electrically conductive tip is used in scanning microwave impedance microscopy (sMIM). sMIM allows for the characterization of the local electrical properties through the analysis of the microwave impedance of the metal-insulator-semiconductor nanocapacitor (nano-MIS capacitor) that is formed by tip and sample.