Post annealing effects on the electrical characteristics of pentacene thin film transistors on flexible substrates.

This work studies the effect of post annealing of pentacene on a flexible substrate through the examination of electrical properties and surface morphologies. It is confirmed that the best performance of devices is achieved when the post annealing temperature is 60 degrees C, since the grain size increases, which decrease grain boundaries caused charge transport limit. We can also confirmed the large threshold voltage shift of device annealed at 60 degrees C that means the lower trap density between channel and insulator interface.

Low-voltage-driven pentacene thin-film transistors with cross-linked poly(4-vinylphenol)/high-k Bi55b3O15 hybrid dielectric for phototransistor.

This paper describes the fabrication of pentacene thin-film transistors (TFTs) with an organic/inorganic hybrid gate dielectric, consisting of cross-linked poly(4-vinylphenol) (PVP) and Bi5Nb3O15. A 300-nm-thick Bi5Nb3O15 dielectric film, grown at room temperature, exhibits a high dielectric constant (high-k) value of 40 but has an undesirable interface with organic semiconductors (OSC). To form better interfaces with OSC, a cross-linked PVP dielectric was stacked on the Bi5Nb3O15 dielectric.