A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory.

In this paper, we propose and analyze a novel interposer channel structure with vertical tabbed vias to achieve high-speed signaling and low-power consumption in high-bandwidth memory (HBM). An analytical model of the self- and mutual capacitance of the proposed interposer channel is suggested and verified based on a 3D electromagnetic (EM) simulation. We thoroughly analyzed the electrical characteristics of the novel interposer channel considering various design parameters, such as the height and pitch of the vertical tabbed via and the gap of the vertical channel.