Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders.

Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel.

A low power, highly efficient, linear, enhanced wideband Class-J mode power amplifier for 5G applications.

In wireless communication networks, the necessity for high-speed data rates has increased in emerging 5G application areas. The Power Amplifier (PA) topologies reported to date achieved desired Power Added Efficiency (PAE) and linearity. However, these harmonically tuned switching PAs are less appealing for broadband applications as they are restricted to narrow bandwidth (BW).

Low energy, low latency and high speed array divider circuit using a shannon theorem based adder cell.

The paper discuss the design of 1-bit full adder circuit using Shannon theorem. This proposed full adder circuit is used as one of the circuit component for implementation of Non- Restoring and Restoring divider circuits. The proposed adder and divider schematics are designed by using DSCH2 CAD tool and their layouts are generated by Microwind 3 VLSI CAD tool.