A Study of the Optimal Logic Combinations of RO-Based PUFs on FPGAs to Maximize Identifiability.

One of the challenges that wireless sensor networks (WSNs) need to address is achieving security and privacy while keeping low power consumption at sensor nodes. Physically unclonable functions (PUFs) offer a challenge-response functionality that leverages the inherent variations in the manufacturing process of a device, making them an optimal solution for sensor node authentication in WSNs. Thus, identifiability is the fundamental property of any PUF.

Oscillator Selection Strategies to Optimize a Physically Unclonable Function for IoT Systems Security.

Physically unclonable functions avoid storing secret information in non-volatile memories and only generate a key when it is necessary for an application, rising as a promising solution for the authentication of resource-constrained IoT devices. However, the need to minimize the predictability of physically unclonable functions is evident. The main purpose of this work is to determine the optimal way to construct a physically unclonable function.

High-Sensitivity Large-Area Photodiode Read-Out Using a Divide-and-Conquer Technique.

In this letter, we present a novel technique to increase the sensitivity of optical read-out with large integrated photodiodes (PD). It consists of manufacturing the PD in several pieces, instead of a single device, and connecting a dedicated transimpedance amplifier (TIA) to each of these pieces. The output signals of the TIAs are combined, achieving a higher signal-to-noise ratio than with the traditional approach.

Application of a MEMS-Based TRNG in a Chaotic Stream Cipher.

In this work, we used a sensor-based True Random Number Generator in order to generate keys for a stream cipher based on a recently published hybrid algorithm mixing Skew Tent Map and a Linear Feedback Shift Register. The stream cipher was implemented and tested in a Field Programmable Gate Array (FPGA) and was able to generate 8-bit width data streams at a clock frequency of 134 MHz, which is fast enough for Gigabit Ethernet applications. An exhaustive cryptanalysis was completed, allowing us to conclude that the system is secure.

Programmable Low-Power Low-Noise Capacitance to Voltage Converter for MEMS Accelerometers.

In this work, we present a capacitance-to-voltage converter (CVC) for capacitive accelerometers based on microelectromechanical systems (MEMS). Based on a fully-differential transimpedance amplifier (TIA), it features a 34-dB transimpedance gain control and over one decade programmable bandwidth, from 75 kHz to 1.2 MHz.

Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays.

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.

A High Performance LIA-Based Interface for Battery Powered Sensing Devices.

This paper proposes a battery-compatible electronic interface based on a general purpose lock-in amplifier (LIA) capable of recovering input signals up to the MHz range. The core is a novel ASIC fabricated in 1.8 V 0.

A programmable plug & play sensor interface for WSN applications.

Cost reduction in wireless sensor networks (WSN) becomes a priority when extending their application to fields where a great number of sensors is needed, such as habitat monitoring, precision agriculture or diffuse greenhouse emission measurement. In these cases, the use of smart sensors is expensive, consequently requiring the use of low-cost sensors. The solution to convert such generic low-cost sensors into intelligent ones leads to the implementation of a versatile system with enhanced processing and storage capabilities to attain a plug and play electronic interface able to adapt to all the sensors used.

Digitally programmable analogue circuits for sensor conditioning systems.

This work presents two current-mode integrated circuits designed for sensor signal preprocessing in embedded systems. The proposed circuits have been designed to provide good signal transfer and fulfill their function, while minimizing the load effects due to building complex conditioning architectures. The processing architecture based on the proposed building blocks can be reconfigured through digital programmability.