Publications by authors named "Sang-Kon Kim"

For vertical interconnect access (VIA) in three-dimensional (3D) structure chips, including those with high bandwidth memory (HBM), shrinking contact holes (C/Hs) using the resist flow process (RFP) represents the most promising technology for low-k1 (where CD=k1λ/NA,CD is the critical dimension, λ is wavelength, and NA is the numerical aperture). This method offers a way to reduce dimensions without additional complex process steps and is independent of optical technologies. However, most empirical models are heuristic methods and use linear regression to predict the critical dimension of the reflowed structure but do not account for intermediate shapes.

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Defect control of extreme ultraviolet (EUV) masks using pellicles is challenging for mass production in EUV lithography because EUV pellicles require more critical fabrication than argon fluoride (ArF) pellicles. One of the fabrication requirements is less than 500 μm transverse deflections with more than 88% transmittance of full-size pellicles (112 mm × 145 mm) at pressure 2 Pa. For the nanometer thickness (thickness/width length (t/L) = 0.

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Although extreme ultraviolet lithography (EUVL) has potential to enable 5-nm half-pitch resolution in semiconductor manufacturing, it faces a number of persistent challenges. Line-edge roughness (LER) is one of critical issues that significantly affect critical dimension (CD) and device performance because LER does not scale along with feature size. For LER creation and impacts, better understanding of EUVL process mechanism and LER impacts on fin-field-effect-transistors (FinFETs) performance is important for the development of new resist materials and transistor structure.

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Although being the optical lithography, the extreme ultraviolet (EUV) lithography with 13.5-nm wavelength is very different from the deep ultraviolet (DUV) lithography with 193-nm wavelength. Hence, the understanding of the complex detailed EUV mechanisms to cause a chemical reaction in chemically amplified resists (CARs) is required to develop EUV resists and exposure process.

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The line-edge roughness (LER) is a critical issue that significantly impacts the critical dimension (CD) because the LER does not scale with the feature size. Hence, the LER influences the device performance with 7-nm and 5-nm patterns. In this study, LER impact on the performance of the fin-field-effect-transistors (FinFETs) are investigated using a compact device method.

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Extreme ultraviolet (EUV) lithography is a prospective technology for the fabrication of integrated chips with critical dimensions (CDs) under 10-nm. However, since chips with similar CDs have similar defect sizes, one of the most critical problems in extreme ultraviolet lithography (EUVL) is mask defect and repair. Defects cause local areas of undesired absorption, reflectivity, or phase change, which ultimately lead to imperfections in the printed image.

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The extreme ultraviolet (EUV) lithography has the potential to enable 5-nm half-pitch resolution in semiconductor manufacturing, but faces a number of persistent challenges. At the 5-nm technology node, a precise process simulator with nanometer accuracy will be required. For a precise simulation, the better understanding the EUV process mechanism is critical for the improvement of resist performance and the development of new resist materials.

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For the wavelength reduction to overcome the diffraction limit of the optical lithography, the surface plasmon lithography (SPL) has lower cost and simpler system configuration than the extreme ultraviolet (EUV) lithography. In this paper, for the below 10-nm critical dimension (CD) as one of critical challenges in the lithography technology, SPL based on the SP interference and metamaterial in bowtie and hexahedron structures is proposed and demonstrated by using computer simulations such as the rigorous coupled-wave analysis (RCWA) method and the finite difference time domain (FDTD) method. For 193-nm wavelength, the minimum FWHM (the full width at half maximum) of the transverse magnetic (TM) intensity in xz plane (and yz plane) is 10-nm (and 7-nm) in a bowtie plasmonic structure.

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For the extreme ultraviolet (EUV) lithography, multilayer (ML) defects such as bump and pit defects can disrupt the phase of reflected field and degrade aerial images on wafer. In this paper, a defect printability and repair simulator (DPRS) is introduced to predict and repair the effect of ML defects in EUV aerial images. DPRS is composed of multilayer growth by using Gaussian function and Stearns's method, mask simulation by using a scattering matrix (S-matrix) analysis method, and projection simulation by using Köhler's illumination.

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For future semiconductor device scaling, self-assembly, directed self-assembly (DSA) of block copolymers (BCPs), is a promising method with simplified processing conditions; however, critical challenge is defect control for fine pattern. Electric field is a method for the defect control. In this paper, for electric field effects to jog defects, the electric field induced self-assembled patterns is modeled and simulated by using the Monte Carlo method of dielectric polymers, the self-consistent-field theory (SCFT), and the Navier-Stokes equation.

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Directed self-assembly (DSA) of block copolymers (BCPs) has become an intense field of study as a complementary technique to conventional lithography for 1×-nm semiconductor patterning. DSA contact hole (C/H) shrinking is a possible implemental technique in the DSA process. In this paper, a DSA C/H shrinking is fully modeled and simulated by using a self-consistent field theory (SCFT).

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For technologies beyond diffraction limit, the plasmonic nanolithography can produce subwavelength structures using the broad beam illumination of the standard photoresist with the visible light. In this study, for the nano-pattern formation, the polarization effects of the transverse magnetic (TM) mode and the transverse electric (TE) mode about diffraction limit and plasmonic phenomena are described on basis of simulation results through the sub-wavelength aperture. TM mode is degraded in diffraction effects but enhanced in plasmonic effects due to the change distribution on the metallic surface and the waveguide resonances in slits.

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Double patterning (DP) and multiple patterning (MP) are techniques employed to extend the useful life of optical lithography through higher density chip transistors. The self-aligned double patterning (SADP) and the self-aligned multiple patterning (SAMP) are promising technologies that can be expanded to 22 nm and 1 x nm patterns for the dynamic random access memory (DRAM) and NAND flash memory devices. It is important to understand how the final pattern is related to each SADP or SAMP step to optimize process parameters and develop those processes.

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Because photoresist has the uncertain triangle relation among the higher resolution, the lower line-edge-roughness (LER) (or line-with-roughness (LWR)), and the improved sensitivity, for below 20-nm pattern formation, this relation makes hard to use the optical lithography. Directed self-assembly (DSA) has been considered as a potential candidate to extend the resolution limit of the optical lithography. The effects of DSA processing and DSA molecular geometry on LER should be well understood in order to meet the ITRS lithographic specifications.

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As the pattern size is cross to virus and molecular sizes, the fabrication cost becomes important. Advantages of the block copolymer lithography (BCPL) through the nanoimprint lithography (NIL) are no diffraction limits, simple and cheap process, and complementary for each of major draw- backs. In this paper, the directed self-assembly lithography of BCP with NIL is successfully modeled and simulated by using the Navier-Stokes equation for the BCP filling process, the multi-thin layer method and the Dill's equation for the UV exposure process, and the self-consistent field theory (SCFT) for the self-assemble process.

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The directed self-assembly (DSA) technology of block copolymers is a candidate for next-generation lithography. The computation model of this lithography can assist in overcoming its challenges. In this paper, a template-assisted self-assembly (DSA graphoepitaxy) is modeled and simulated in a molecular scale to reduce the process complexity.

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Photoresist lithography has been applied to the fabrication of micro/nano devices, such as microfluidic structures, quantum dots, and photonic devices, in MEMS (micro-electro mechanical systems) and NEMS (nano-electro-mechanical systems). In particular, nano devices can be expected to present different physical phenomena due to their three-dimensional (3D) structure. The flexible 3D micro/nano fabrication technique and its process simulation have become among the major topics needed to understand nano-mechanical phenomena.

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