Quantitative three-dimensional carrier mapping in nanowire-based transistors using scanning spreading resistance microscopy.

The performance of nanoelectronic devices critically depends on the distribution of charge carriers inside such structures. High-vacuum scanning spreading resistance microscopy (HV-SSRM) has established as the method of choice for quantitative 2D-carrier mapping in nanoscale devices during the last decade. However, due to the 3D-nature of these nanoscale device architectures, dopant incorporation and dopant diffusion mechanisms can vary for any of the three dimensions, depending on the particular processes used.

Observation of diameter dependent carrier distribution in nanowire-based transistors.

The successful implementation of nanowire (NW) based field-effect transistors (FET) critically depends on quantitative information about the carrier distribution inside such devices. Therefore, we have developed a method based on high-vacuum scanning spreading resistance microscopy (HV-SSRM) which allows two-dimensional (2D) quantitative carrier profiling of fully integrated silicon NW-based tunnel-FETs (TFETs) with 2 nm spatial resolution. The key elements of our characterization procedure are optimized NW cleaving and polishing steps, the use of in-house fabricated ultra-sharp diamond tips, measurements in high vacuum and a dedicated quantification procedure accounting for the Schottky-like tip-sample contact affected by surface states.