Publications by authors named "P Fiorenza"

Objectives: Systemic Sclerosis (SSc) is characterized by widespread microangiopathy and fibrosis of skin and visceral organs. Left ventricle involvement is usually subclinical, characterized by systolic and/or diastolic dysfunction. The global longitudinal strain (GLS), a validated and reliable technique for the measurement of ventricular longitudinal deformation by means of echocardiography, may detect subclinical systolic dysfunction of SSc myocardium.

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This paper presents a reliability study of a conventional 650 V SiC planar MOSFET subjected to pulsed HTRB (High-Temperature Reverse Bias) stress and negative HTGB (High-Temperature Gate Bias) stress defined by a TCAD static simulation showing the electric field distribution across the SiC/SiO interface. The instability of several electrical parameters was monitored and their drift analyses were investigated. Moreover, the shift of the onset of the Fowler-Nordheim gate injection current under stress conditions provided a reliable method to quantify the trapped charge inside the gate oxide bulk, and it allowed us to determine the real stress conditions.

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In this paper, we present the preparation of few-layer MoS films on single-crystal sapphire, as well as on heteroepitaxial GaN templates on sapphire substrates, using the pulsed laser deposition (PLD) technique. Detailed structural and chemical characterization of the films were performed using Raman spectroscopy, X-ray photoelectron spectroscopy, X-ray diffraction measurements, and high-resolution transmission electron microscopy. According to X-ray diffraction studies, the films exhibit epitaxial growth, indicating a good in-plane alignment.

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Metal-oxide-semiconductor (MOS) capacitors with AlO as a gate insulator are fabricated on cubic silicon carbide (3C-SiC). AlO is deposited both by thermal and plasma-enhanced Atomic Layer Deposition (ALD) on a thermally grown 5 nm SiO interlayer to improve the ALD nucleation and guarantee a better band offset with the SiC. The deposited AlO/SiO stacks show lower negative shifts of the flat band voltage V (in the range of about -3 V) compared with the conventional single SiO layer (in the range of -9 V).

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The historical scaling down of electronics devices is no longer the main goal of the International Roadmap for Devices and Systems [...

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