Carrier Trap Density Reduction at SiO/4H-Silicon Carbide Interface with Annealing Processes in Phosphoryl Chloride and Nitride Oxide Atmospheres.

The electrical and physical properties of the SiC/SiO interfaces are critical for the reliability and performance of SiC-based MOSFETs. Optimizing the oxidation and post-oxidation processes is the most promising method of improving oxide quality, channel mobility, and thus the series resistance of the MOSFET. In this work, we analyze the effects of the POCl annealing and NO annealing processes on the electrical properties of metal-oxide-semiconductor (MOS) devices formed on 4H-SiC (0001).