Packet clock recovery using a bismuth oxide fiber-based optical power limiter.

We demonstrate an optical clock recovery circuit that extracts the line rate component on a per packet basis from short data packets at 40Gb/s. The circuit comprises a Fabry-Perot filter followed by a novel power limiting configuration, which in turn consists of a 5m highly nonlinear bismuth oxide fiber in cascade with an optical bandpass filter. Both experimental and simulation-based results are in close agreement and reveal that the proposed circuit acquires the timing information within only a small number of bits, yielding a packet clock for every respective data packet.

Packet-level synchronization scheme for optical packet switched network nodes.

We demonstrate an all-optical, self-synchronization scheme for optical packet switched network nodes. It provides both the packet clock signal and the packet beginning, marker pulse. The circuit uses two hybridly integrated MZI switches and has been evaluated with synchronous, asynchronous and variable length, data packets at 10 Gb/s.

Compact all-optical packet clock and data recovery circuit using generic integrated MZI switches.

We present and evaluate a compact, all-optical Clock and Data Recovery (CDR) circuit based on integrated Mach Zehnder interferometric switches. Successful operation for short packet-mode traffic of variable length and phase alignment is demonstrated. The acquired clock signal rises within 2 bits and decays within 15 bits, irrespective of packet length and phase.